Integrating volterra series model and deep neural networks to equalize nonlinear power amplifiers

Abstract

The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Nonlinear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.

Claims

1. A distortion-compensating processor, comprising: at least one automated processor configured to decompose a non-linearly distorted signal derived from an information signal, received from a channel having a channel non-linear distortion into a truncated series expansion of at least third order with memory comprising a series of terms, each term representing incremental non-linearity order and associated delay; an adaptive multi-layer feedforward deep neural network comprising a plurality of hidden layers, and at least one dropout layer, receiving as inputs the series of terms, and producing an equalized output signal; and an output port configured to present the equalized output signal, the multi-layer feedforward deep neural network being trained with respect to the channel non-linear distortion associated with communication of a series of symbols using training data comprising the series of terms, to equalize the signal, the multi-layer feedforward deep neural network being configured to receive the respective terms associated with incremental non-linearity orders and associated delay values, and to selectively produce the equalized output signal, representing the information signal wherein the channel non-linear distortion is reduced.

2. The distortion-compensating processor according to claim 1, wherein the training data comprises a set of small amplitude training signals to estimate a channel response and a set of large amplitude training signals to estimate a power amplifier non-linearity.

3. The distortion-compensating processor according to claim 1, wherein the information signal is distorted by amplification by a radio frequency power amplifier and transmission through a radio frequency communication channel, wherein the non-linearly distorted signal is received by the at least one automated processor from a radio receiver.

4. The distortion-compensating processor according to claim 1, wherein the series expansion of at least third order with memory comprises a Volterra series expansion.

5. The distortion-compensating processor according to claim 4, wherein the terms of the Volterra series expansion are defined by: $y\left(n\right)=\underset{d=0}{\overset{D}{.Math.}}\underset{k=0}{\overset{P}{.Math.}}{b}_{\mathrm{kd}}x\left(n-d\right){.Math.x\left(n-d\right).Math.}^{k-1};$ and the multi-layer feedforward neural network is trained with respect to the channel non-linear distortion to produce: $\left(n\right)=\underset{k=1}{\overset{P}{.Math.}}\underset{d_1=0}{\overset{D}{.Math.}}.Math.\underset{d_k=0}{\overset{D}{.Math.}}{f}_{d_1,.Math.,d_k}\underset{i=1}{\overset{k}{.Math.}}r\left(n-d_i\right),$ where: y(n) represents the non-linearly distorted signal; z(n) is the equalized output signal; d is a memory depth parameter; D is a total memory length; k is a respective nonlinearity order; P is a total nonlinearity order; k is a nonlinear order; b.sub.kd are nonlinear response parameters; and r(n) is a response of the channel to the non-linearly distorted signal y(n).

6. The distortion-compensating processor according to claim 1, wherein: x(n) is a signal sequence representing information in the non-linearly distorted signal y(n) distorted by an analog process within a channel h; $r\left(n\right)=\underset{=0}{\overset{L}{.Math.}}{h}_{}y\left(n-\right)+v\left(n\right)$ is a response signal sequence; r(n) is stacked together into M+1 dimensional vectors r(n)=[r(n), . . . , r(nM)].sup.T, where ().sup.T denotes transpose, such that r(n)=HG(n)x(n)+v(n); h.sub. is a set of finite-impulse response channel coefficients; is an equalization delay; v(n) is an additive white Gaussian noise component signal sequence; H is an (M+1)(M+L+1) dimensional channel matrix $H=\left[\begin{array}{ccccc}{h}_o& .Math.& h_L& & \\ & & & & \\ & & h_o& .Math.& h_L\end{array}\right];$ $G\left(n\right)=\mathrm{diag}\left\{V_{y\left(n\right)}{e}^{j{}_{y\left(n\right)}},.Math.,V_{n\left(y-M-L\right)}{e}^{j{}_{y\left(n-M-L\right)}}\right\}$ is an (M+L+1)(M+L+1) dimensional diagonal matrix of the nonlinear responses, x(n)=[x(n), . . . , x(nML)].sup.T, and v(n)=[v(n, . . . , v(nM)].sup.T; .sup.T=G(n)[.sub.0, . . . , .sub.M], where [.sub.0, . . . , .sub.M]H[0, . . . , 1, . . . , 0] is computed by the equalizer to equalize the channel; $G^{}\left(n\right)\frac{1}{V_{y\left(n-d\right)}}{e}^{-j{}_{y\left(n-d\right)}}$ is computed by equalizer to equalize to equalize the analog process; {circumflex over (r)}(n) is a sequence after linear channel equalization; z(n)=.sup.Tr(n)x(nd) represents the output signal with equalization delay d; $z\left(n\right)=\underset{d=0}{\overset{D}{.Math.}}\underset{p=0}{\overset{P}{.Math.}}{g}_{kd}\stackrel{}{r}\left(n-d\right){.Math.\stackrel{}{r}\left(n-d\right).Math.}^{k-1}$ is a Volterra series model of the equalizer with coefficients g.sub.kd such that z(n)x(n) for some equalization delay ; g.sub.kd are coefficients determined according to $\underset{\left\{g_{kd}\right\}}{\min }\underset{n=L}{\overset{N}{.Math.}}{.Math.x\left(n-L\right)-\underset{d=0}{\overset{D}{.Math.}}\underset{k=1}{\overset{P}{.Math.}}{g}_{kd}\stackrel{}{r}\left(n-d\right){.Math.\stackrel{}{r}\left(n-d\right).Math.}^{k-1}.Math.}^2$ with training symbols x(n) and received samples {circumflex over (r)}(n); $z\left(n\right)=\arg {\min }_{x\left(n\right)}{.Math.\stackrel{}{r}\left(n\right)-V_y{e}^{j{}_y}x\left(n\right).Math.}^2$ is a maximum likelihood estimation operator for the output signal comprising a nonlinear equalization output signal sequence having reduced distortion; V.sub.y is an amplitude of a non-linearly distorted signal sequence y(n); .sub.y is a phase change of the non-linearly distorted signal sequence y(n); and the multi-layer feedforward neural network is trained to determine the channel coefficients h, analog process responses V.sub.y, .sub.y, and the channel equalizer .sup.T.

7. The distortion-compensating processor according to claim 6, wherein: $$\begin{gathered} \begin{array}{cc}\mathrm{vector}a={\left[g_{00},g_{01},.Math.,g_{PD}\right]}^T,\mathrm{vector}x={\left[x\left(0\right);.Math.,x\left(N-L\right)\right]}^T,\mathrm{vector}B=\left[\begin{array}{cccc}\hat{r}\left(L\right)& \hat{r}\left(L\right).Math.\hat{r}\left(L\right).Math.& .Math.& \hat{r}\left(L-D\right){.Math.\hat{r}\left(L-D\right).Math.}^{P-1}\\ .Math.& & & .Math.\\ \hat{r}\left(N\right)& \hat{r}\left(N\right).Math.\hat{r}\left(N\right).Math.& .Math.& \hat{r}\left(N-D\right){.Math.\hat{r}\left(N-D\right).Math.}^{P-1}\end{array}\right],\mathrm{and} \\ \underset{\left\{g_{kd}\right\}}{\min }\underset{n=L}{\overset{N}{.Math.}}{.Math.x\left(n-L\right)-\underset{d=0}{\overset{D}{.Math.}}\underset{k=1}{\overset{P}{.Math.}}{g}_{kd}\stackrel{}{r}\left(n-d\right){.Math.\stackrel{}{r}\left(n-d\right).Math.}^{k-1}.Math.}^2\underset{a}{\min }{.Math.x-\mathrm{Ba}.Math.}^2,\mathrm{having}\mathrm{solution}a=B^{+}x,\mathrm{where}{B}^{+}={\left(B^{H}B\right)}^{-1}B\mathrm{is}\mathrm{the}\mathrm{pseudo}\mathrm{inverse}\mathrm{of}\mathrm{the}\mathrm{matrix}B.& \end{array} \end{gathered}$$

8. The distortion-compensating processor according to claim 1, wherein the truncated series expansion of at least third order with memory comprises at least fifth order terms, and the deep multi-layer feedforward neural network has at least two convolutional network layers.

9. The distortion-compensating processor according to claim 1, wherein the deep multi-layer feedforward neural network comprises at least three hidden layers, each hidden layer comprising at least 10 feature maps, and a fully connected layer subsequent to the at least three hidden layers.

10. The distortion-compensating processor according to claim 1, wherein the non-linearly distorted signal comprises a frequency division multiplexed radio frequency modulated set of signals representing the information signal distorted by a radio frequency power amplifier; further comprising a frequency division multiplexed radio frequency signal demodulator configured to demodulate the equalized output signal as the set of symbols.

11. A method of compensating for a distortion, comprising: decomposing a non-linearly distorted signal received from a channel having a channel non-linear distortion into a truncated series expansion of at least third order with memory, based on an information signal communicated through the channel, the decomposition comprising a series of terms, each term representing incremental non-linearity order and associated delay, using at least one automated processor; equalizing the non-linearly distorted signal with an automated equalizer comprising a multi-layer feedforward deep neural network comprising a plurality of hidden layers and at least one dropout layer, by receiving coefficients of respective terms associated with respective incremental non-linearity orders and associated delay by the automated equalizer, and producing selectively from the equalizer an output signal representing the information signal wherein the channel non-linear distortion is reduced; and updating the multi-layer feedforward deep neural network to reduce error of the output signal with respect to the information signal.

12. The method according to claim 11, wherein the non-linearly distorted signal comprises a frequency division multiplexed signal amplified and distorted by a radio frequency power amplifier, received though a radio frequency receiver, further comprising demodulating information contained within the frequency division multiplexed signal from the output signal.

13. The method according to claim 11, further comprising outputting the output signal, wherein the truncated series expansion of at least third order with memory comprises at least fifth order terms and the multi-layer feedforward deep neural network comprises at least two hidden layers.

14. The method according to claim 11, wherein the series expansion of at least third order with memory comprises a Volterra series expansion having terms defined by: $y\left(n\right)=\underset{d=0}{\overset{D}{.Math.}}\underset{k=0}{\overset{P}{.Math.}}{b}_{kd}x\left(n-d\right){.Math.x\left(n-d\right).Math.}^{k-1};$ and the multi-layer feedforward deep neural network is trained with respect to the channel non-linear distortion to produce: $z\left(n\right)=\underset{k=1}{\overset{P}{.Math.}}\underset{d_1=0}{\overset{P}{.Math.}}.Math.\underset{d_k=0}{\overset{D}{.Math.}}{f}_{d_1,.Math.,d_k}\underset{i=1}{\overset{k}{.Math.}}r\left(n-d_i\right),$ where: y(n) represents the non-linearly distorted signal; z(n) is the equalized output signal; d is a memory depth parameter; D is a total memory length; k is a respective nonlinearity order; P is a total nonlinearity order; k is a nonlinear order; b.sub.kd are nonlinear response parameters; and r(n) is a response of the channel to the non-linearly distorted signal y(n).

15. The method according to claim 11, wherein: x(n) is a signal sequence representing information in the signal y(n) distorted by an analog process within a channel h; $r\left(n\right)=\underset{=0}{\overset{L}{.Math.}}{h}_{}y\left(n-\right)+v\left(n\right)$ is a response signal sequence; r(n) is stacked together into M+1 dimensional vectors r(n)=[r(n), . . . , r(nM)].sup.T, where ().sup.T denotes transpose, such that r(n)=HG(n)x(n)+v(n); h.sub. is a set of finite-impulse response channel coefficients; is an equalization delay; v(n) is an additive white Gaussian noise component signal sequence; H is an (M+1)(M+L+1) dimensional channel matrix $H=\left[\begin{array}{ccccc}{h}_o& .Math.& h_L& & \\ & & & & \\ & & h_o& .Math.& h_L\end{array}\right];$ $G\left(n\right)=\mathrm{diag}\left\{V_{y\left(n\right)}{e}^{j{}_{y\left(n\right)}},.Math.,V_{n\left(y-M-L\right)}{e}^{j{}_{y\left(n-M-L\right)}}\right\}$ is an (M+L+1) (M+L+1) dimensional diagonal matrix of the nonlinear responses, x(n)=[x(n), . . . , x(nML].sup.T, and v(n)=[v(n, . . . , v(nM)].sup.T; .sup.T=G(n)[.sub.0, . . . , .sub.M], where [.sub.0, . . . , .sub.M]H[0, . . . , 1, . . . , 0] is computed by the equalizer to equalize the channel; $G^{}\left(n\right)=\frac{1}{V_{y\left(n-d\right)}}{e}^{-j{}_{y\left(n-d\right)}}$ is computed by equalizer to equalize to equalize the analog process; {circumflex over (r)}(n) is a sequence after linear channel equalization; Z(n)=.sup.Tr(n)x(nd) represents the output signal with equalization delay d; $z\left(n\right)=\underset{d=0}{\overset{D}{.Math.}}\underset{p=0}{\overset{P}{.Math.}}{g}_{kd}\stackrel{}{r}\left(n-d\right){.Math.\stackrel{}{r}\left(n-d\right).Math.}^{k-1}$ is a Volterra series model of the equalizer with coefficients g.sub.kd such that z(n)x(n) for some equalization delay ; g.sub.kd are coefficients determined according to $\underset{\left\{g_{kd}\right\}}{\min }\underset{n=L}{\overset{N}{.Math.}}{.Math.x\left(n-L\right)-\underset{d=0}{\overset{D}{.Math.}}\underset{k=1}{\overset{P}{.Math.}}{g}_{kd}\stackrel{}{r}\left(n-d\right){.Math.\stackrel{}{r}\left(n-d\right).Math.}^{k-1}.Math.}^2$ with training symbols x(n) and received samples {circumflex over (r)}(n); z(n)=arg min.sub.x(n)|{circumflex over (r)}(n)V.sub.ye.sup.jx(n)|.sup.2 is a maximum likelihood estimation operator for the output signal comprising a non-linear equalization output signal sequence having reduced distortion; V.sub.y is an amplitude of a signal sequence y(n); .sub.y is a phase change of the signal sequence y(n); and the multi-layer feedforward neural network is trained to determine the channel coefficients h, analog process responses V.sub.y, .sub.y, and the channel equalizer .sup.T.

16. The method according to claim 11, wherein the multi-layer feedforward deep neural network comprises at least one convolutional layer, followed by a fully connected layer with dropout comprising the at least one dropout layer, and an output layer.

17. The method according to claim 11, wherein the multi-layer feedforward deep neural network comprises at least three one-dimensional convolutional layers each comprising at least 10 feature maps, followed by a first fully-connected layer with the at least one dropout layer provided for regularization, and a second fully-connected layer which produces the output with respect to a delay, the multi-layer feedforward deep neural network producing an output tensor having two dimensions, wherein the at three one-dimensional convolutional layers and the first fully connected layer use a sigmoid activation function, and the fully connected output layer uses a linear activation function.

18. A non-linear distortion-compensating processor, comprising: an input signal processor configured to decompose a received non-linearly distorted signal based on an information signal communicated through a channel, into a truncated Volterra series expansion, the truncated Volterra series expansion comprising a series of terms, each term comprising a sum of multidimensional convolutions of at least third order each with an associated time delay component; and a multi-layer feedforward deep neural network comprising a plurality of hidden neural network layers comprising at least one convolutional neural network layer and at least one dropout layer, trained with respect to a non-linear distortion of the information signal represented in the non-linearly distorted signal, and updated dependent on equalizer error, to receive the series of terms of the truncated Volterra series expansion, and to selectively produce an output signal representing the non-linearly distorted signal at least partially compensated for the non-linear distortion.

19. The non-linear distortion-compensating processor according to claim 18, further comprising a demodulator configured to demodulate information modulated in the non-linearly distorted signal, wherein the non-linearly distorted signal comprises a frequency division multiplexed signal distorted by a power amplifier and a communication channel.

20. The non-linear distortion-compensating processor according to claim 18, wherein the multi-layer feedforward deep neural network comprises a plurality of convolutional layers, each convolutional layer comprising at least 10 feature maps, followed by a first fully connected layer with the at least one dropout layer provided for regularization, and a second fully connected layer for output, wherein the plurality of convolutional layers and the first fully connected layer use a non-linear activation function, and the second fully connected layer uses a linear activation function.

21. A method of compensating for a distortion, comprising: decomposing a signal received from a channel having a channel non-linear distortion into a truncated series expansion of at least third order with memory, using at least one automated processor; and equalizing the signal with an automated equalizer comprising a multi-layer feedforward deep neural network trained having at least one convolutional layer, followed by a fully connected layer with dropout, and an output layer, with respect to the channel non-linear distortion, by receiving terms of the truncated series expansion of at least third order with memory by the automated equalizer, and producing selectively from the equalizer an output representing the signal wherein the channel non-linear distortion is reduced.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a system block diagram with nonlinear power amplifier and deep neural network equalizer.

(2) FIG. 2 shows a block diagram of DNN equalizer.

(3) FIGS. 3A-3D show constellations of 16 QAM over a simulated PA. FIG. 3A: received signal. FIG. 3B: Volterra equalizer output. FIG. 3C: time-delayed NN output. FIG. 3D: Volterra+NN output.

(4) FIGS. 4A-4D show constellation of 16 QAM over a real PA. FIG. 4A: received signal. FIG. 4B: Volterra equalizer output. FIG. 4C: time-delayed NN output. FIG. 4D: Volterra+NN output.

(5) FIG. 5 shows a comparison of three equalization methods for 16-QAM under various NLD levels.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Volterra-Based DNN Equalizer

(6) The present technology therefore employs deep neural networks to implement the nonlinear equalizer in the receiver, which can mitigate the nonlinear effects of the received signals due to not only PAs but also nonlinear channels and propagations. The architecture of the DNN equalizer is shown in FIG. 2, which shows an input X, which undergoes a series of three 1-d convolutions, and FC (fully-connected) dropout, to produce the output Y.

(7) Different from [10], multi-layer convolutional neural networks (CNNs) are employed. Different from conventional neural network predistorters proposed in [6], neural networks are used as equalizers at the receivers. Different from conventional neural network equalizers such as those proposed in [14] [15], in the present DNN equalizer, not only the linear delayed samples r(n), but also the CNN and the input features in X are used. The Volterra series models are applied to create input features.

(8) We can assume that the linear channel H has already been equalized by a linear equalizer, whose output signal is r(n). In fact, this equalization is not required, but simplifies the presentation of the analysis.

(9) According to Volterra series representation of nonlinear functions, the input-output response of the nonlinear equalizer can be written as

(10) $\begin{array}{cc}\left(n\right)=\underset{k=1}{\overset{P}{.Math.}}\underset{d_1=0}{\overset{D}{.Math.}}.Math.\underset{d_k=0}{\overset{D}{.Math.}}{f}_{d_1,.Math.,d_k}\underset{i=1}{\overset{k}{.Math.}}r\left(n-d_i\right).& \left(20\right)\end{array}$

(11) One of major problems is that the number of coefficients .sub.d.sub.1.sub., . . . , d.sub.k increases exponentially with the increase of memory length D and nonlinearity order P. There are many different ways to develop more efficient Volterra series representations with reduced number of coefficients. For example, [23], exploits the fact that higher-order terms do not contribute significantly to the memory effects of PAs to reduce the memory depth d when the nonlinearity order k increases.

(12) This technique can drastically reduce the total number of coefficients. In [24] [25] and [26], a dynamic deviation model was developed to reduce the full Volterra series model (20) to the following simplified one:

(13) 0$\left(n\right)={}_s\left(n\right)+{}_d\left(n\right)=\underset{k=1}{\overset{P}{.Math.}}{f}_{k,0}{r}^k\left(n\right)+\underset{k=1}{\overset{P}{.Math.}}\underset{j=1}{\overset{k}{.Math.}}{r}^{k-j}\left(n\right)\underset{d_1=0}{\overset{D}{.Math.}}.Math.\underset{d_j=d_{j-1}}{\overset{D}{.Math.}}{f}_{k,j}\underset{i=1}{\overset{j}{.Math.}}r\left(n-d_i\right)$

(14) where .sub.s(n) is the static term, and .sub.d(n) is the dynamic term that includes all the memory effects. We can see that the total number of coefficients can be much reduced by controlling the dynamic order j which is a selectable parameter.

(15) We construct the input features of the DNN based on the model (21). Corresponding to the static term .sub.s(n), we change it to:

(16) ${\hat{}}_s\left(n\right)=\underset{1kP}{.Math.}{f}_{k,0}r\left(n\right){.Math.r\left(n\right).Math.}^{k-1}.$

(17) The reason that (22) changes r.sup.k(n) to r(n)|r(n)|.sup.k-1 is that only the signal frequency within the valid passband is interested. This means the input feature vector X should include terms r(n)|r(n)|.sup.k-1. Similarly, corresponding to the dynamic term .sub.d(n), we need to supply r.sup.k-j(n).sub.i1.sup.jr(nd.sub.i) in the features where half of the terms r(n) and r(nd.sub.i) should be conjugated. For simplicity, in the DNN equalizer, the vector X includes r(nq)|r(nq)|.sup.k-1 for some q and k.

(18) By applying Volterra series components directly as features of the input X, the DNN can develop more complex nonlinear functions with a fewer number of hidden layers and a fewer number of neurons. This will also make the training procedure converge much faster with much less training data.

(19) In FIG. 2, the input X is a tensor formed by the real and imaginary parts of r(nq)|r(n|q).sup.k-1 with appropriate number of delays q and nonlinearities k. There are three single dimension convolutional layers, each with 20 or 10 feature maps. After a dropout layer for regularization, this is followed by a fully-connected layer with 20 neurons. Finally, there is a fully-connected layer to form the output tensor Y which has two dimensions. The output Y is used to construct the complex (n), where (n)={circumflex over (x)}(nd) for some appropriate delay d. All the convolutional layers and the first fully connected layer use the sigmoid activation function, while the output layer uses the linear activation function. The mean square error loss function L.sup.loss=E[|x(nd)(n)|.sup.2] is used, where (n) is replaced by Y and x(nd) is replaced by training data labels.

Experiment Evaluations

(20) Experiments are presented on applying the Volterra series based DNN equalizer (Volterra+NN) for nonlinear PA equalization. The (Volterra+NN) scheme with the following equalization methods: a Volterra series-based equalizer (Volterra) and a conventional time-delay neural network equalizer (NN). The performance metrics are mean square error (MSE)
{square root over (E[|z(n)x(nd)|.sup.2]/E[|x(nd)|.sup.2])}

(21) and symbol error rate (SER).

(22) Both simulated signals and real measurement signals were employed. To generate simulated signals, a Doherty nonlinear PA model consisting of 3rd and 5th order nonlinearities was employed. Referring to (2), the coefficients b.sub.k,q were
b.sub.0,0:2={1.0513+0.0904j,0.0680.0023j,0.02890.0054j}
b.sub.2,0:2={0.05420.29j,0.2234+0.2317j,0.06210.0932j}
b.sub.4,0:2={0.96570.7028j,0.24510.3735j,0.1229+0.1508j},

(23) which was used in [5] to simulate a 5th order dominant nonlinear distortion derived from PA devices used in the satellite industry. For real measurement, our measurement signals were obtained from PA devices used in the cable TV (CATV) industry, which are typically dominated by 3.sup.rd order nonlinear distortion (NLD). Various levels of nonlinear distortion, in terms of dBc, were generated by adjusting the PAs.

(24) For the Volterra equalizer, the approximate response of the nonlinear equalizer with delays including 8 pre- and post-main taps and with nonlinearities including even and odd order nonlinearity up to the 5th order was employed. To determine the values of the Volterra coefficients, N=4; 096 training symbols were transmitted through the PA and then collected the noisy received samples r(n).

(25) For the conventional time-delay NN equalizer, a feedforward neural network with an 80-dimensional input vector X and 5 fully-connected hidden layers with 20, 20, 10, 10, 10 neurons, respectively, was applied.

(26) FIG. 3 shows the constellation and MSE of the equalizer's outputs. It can be seen that the proposed scheme provides the best performance.

(27) FIG. 4 shows the constellation of 16 QAM equalization over the real PA. The corresponding SER were 0.0067, 0.0027, 0.00025, respectively. It can be seen that the Volterra+NN scheme has the best performance.

(28) FIG. 5 provides MSE measurements for 16-QAM under various nonlinear distortion level dBc. For each 1 dB increase in NLD, the resultant MSE is shown for the Measured, Volterra, NN, and the proposed Volterra+NN cases. MSE reduction diminishes appreciably as modulation order increases from QPSK to 64-QAM, but small improvements in MSE have been observed lead to appreciable SER improvement, especially for more complex modulation orders. The 4,096 symbol sample sizes have limited the measurements to a minimum measurable 0.000244 SER, which represents 1 symbol error out of 4,096 symbols.

(29) Table 2 summarizes equalization performance, which shows the averaged percent reduction/improvement in MSE and SER from the NLD impaired data for multiple modulation orders. Note that 0% SER improvement for QPSK was because the received signal's SER was already very low.

(30) TABLE-US-00002 TABLE 2 EQ-MSE/SER improvement in percentage over measured NLD Volterra NN Volterra + NN MSE SER MSE SER MSE SER 64-QAM 16% 26% 10% 25% 42% 44% 16-QAM 41% 2% 35% 6% 85% 28% QPSK 57% 0% 100% 0% 100% 0% Average 38% 9% 48% 10% 76% 24%

(31) The nonlinear equalization scheme presented by integrating the Volterra series nonlinear model with deep neural networks yields superior results over conventional nonlinear equalization approaches in mitigating nonlinear power amplifier distortions. It finds application for many 5G communication scenarios.

(32) The technology may be implemented as an additional component in a receiver, or within the digital processing signal chain of a modern radio. A radio is described in US 20180262217, expressly incorporated herein by reference.

(33) In an implementation, a base station may include a SDR receiver configured to allow the base station to operate as an auxiliary receiver. In an example implementation, the base station may include a wideband receiver bank and a digital physical/media access control (PHY/MAC) layer receiver. In this example, the SDR receiver may use a protocol analyzer to determine the protocol used by the source device on the uplink to the primary base station, and then configure the digital PHY/MAC layer receiver for that protocol when operating as art auxiliary receiver. Also, the digital PHY/MAC layer receiver may be configured to operate according to another protocol when operating as a primary base station. In another example, the base station may include a receiver hank for a wireless system, for example, a fifth Generation (5G) receiver bank, and include an additional receiver having SDR configurable capability. The additional receiver may be, for example, a digital Wi-Fi receiver configurable to operate according to various Wi-Fi protocols. The base station may use a protocol analyzer to determine the particular Wi-Fi protocol used by the source device on the uplink to the primary base station. The base station may then configure the additional receiver as the auxiliary receiver for that Wi-Fi protocol.

(34) Depending on the hardware configuration, a receiver may be used to flexibly provide uplink support in systems operating according to one or more protocols such as the various IEEE 802.11 Wi-Fi protocols, 3.sup.rd Generation Cellular (3G), 4.sup.th Generation Cellular (4G) wide band code division multiple access (WCDMA), Long Term Evolution (LTE) Cellular, and 5.sup.th generation cellular (5G).

(35) See, 5G References, infra.

(36) Processing unit may comprise one or more processors, or other control circuitry or any combination of processors and control circuitry that provide, overall control according to the disclosed embodiments. Memory may be implemented as any type of as any type of computer readable storage media, including non-volatile and volatile memory.

(37) The example embodiments disclosed herein may be described in the general context of processor-executable code or instructions stored on memory that may comprise one or more computer readable storage media (e.g., tangible non-transitory computer-readable storage media such as memory). As should be readily understood, the terms computer-readable storage media or non-transitory computer-readable media include the media for storing of data, code and program instructions, such as memory, and do not include portions of the media for storing transitory propagated or modulated data communication signals.

(38) While the functionality disclosed herein has been described by illustrative example using descriptions of the various components and devices of embodiments by referring to functional blocks and processors or processing units, controllers, and memory including instructions and code, the functions and processes of the embodiments may be implemented and performed using any type of processor, circuit, circuitry or combinations of processors and or circuitry and code. This may include, at least in part, one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-a-chip systems (SOCs), complex programmable logic devices (CPLDs), etc. Use of the term processor or processing unit in this disclosure is mean to include all such implementations.

(39) The disclosed implementations include a receiver, one or more processors in communication with the receiver, and memory in communication with the one or more processors, the memory comprising code that, when executed, causes the one or more processors to control the receiver to implement various features and methods according to the present technology.

(40) Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example embodiments, implementations, and forms of implementing the claims and these example configurations and arrangements may be changed significantly without departing from the scope of the present disclosure. Moreover, although the example embodiments have been illustrated with reference to particular elements and operations that facilitate the processes, these elements, and operations may be combined with or, be replaced by, any suitable devices, components, architecture or process that achieves the intended functionality of the embodiment. Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications a falling within the scope of the appended claims.

REFERENCES

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Volterra Series References

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Filter References

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Volterra Series Patents

(45) U.S. Pat. Nos. and Published Patent Application Nos.: U.S. Pat. Nos. 4,615,038; 4,669,116; 4,870,371; 5,038,187; 5,309,481; 5,329,586; 5,424,680; 5,438,625; 5,539,774; 5,647,023; 5,692,011; 5,694,476; 5,744,969; 5,745,597; 5,790,692; 5,792,062; 5,815,585; 5,889,823; 5,924,086; 5,938,594; 5,991,023; 6,002,479; 6,005,952; 6,064,265; 6,166,599; 6,181,754; 6,201,455; 6,201,839; 6,236,837; 6,240,278; 6,288,610; 6,335,767; 6,351,740; 6,381,212; 6,393,259; 6,406,438; 6,408,079; 6,438,180; 6,453,308; 6,504,885; 6,510,257; 6,512,417; 6,532,272; 6,563,870; 6,600,794; 6,633,208; 6,636,115; 6,668,256; 6,687,235; 6,690,693; 6,697,768; 6,711,094; 6,714,481; 6,718,087; 6,775,646; 6,788,719; 6,812,792; 6,826,331; 6,839,657; 6,850,871; 6,868,380; 6,885,954; 6,895,262; 6,922,552; 6,934,655; 6,940,790; 6,947,857; 6,951,540; 6,954,476; 6,956,433; 6,982,939; 6,992,519; 6,999,201; 6,999,510; 7,007,253; 7,016,823; 7,061,943; 7,065,511; 7,071,797; 7,084,974; 7,092,043; 7,113,037; 7,123,663; 7,151,405; 7,176,757; 7,209,566; 7,212,933; 7,236,156; 7,236,212; 7,239,301; 7,239,668; 7,251,297; 7,268,620; 7,272,594; 7,286,009; 7,295,961; 7,304,591; 7,305,639; 7,308,032; 7,333,559; 7,348,844; 7,400,807; 7,403,884; 7,412,469; 7,423,699; 7,436,883; 7,443,326; 7,489,298; 7,512,900; 7,542,518; 7,551,668; 7,570,856; 7,571,401; 7,576,606; 7,589,725; 7,590,518; 7,602,240; 7,606,539; 7,610,183; 7,657,405; 7,720,232; 7,720,236; 7,728,658; 7,729,446; 7,733,177; 7,746,955; 7,755,425; 7,760,887; 7,773,692; 7,774,176; 7,795,858; 7,796,960; 7,808,315; 7,812,666; 7,821,337; 7,821,581; 7,822,146; 7,826,624; 7,847,631; 7,852,913; 7,853,443; 7,864,881; 7,873,172; 7,885,025; 7,885,797; 7,889,007; 7,894,788; 7,895,006; 7,899,416; 7,902,925; 7,903,137; 7,924,942; 7,929,375; 7,932,782; 7,970,150; 7,970,151; 7,979,837; 7,991,073; 7,991,167; 7,995,674; 8,005,858; 8,023,668; 8,031,882; 8,039,871; 8,045,066; 8,046,199; 8,065,060; 8,089,689; 8,105,270; 8,139,630; 8,148,983; 8,149,950; 8,160,191; 8,165,854; 8,170,508; 8,185,853; 8,193,566; 8,195,103; 8,199,399; 8,213,880; 8,244,787; 8,260,732; 8,265,583; 8,270,530; 8,294,605; 8,295,790; 8,306,488; 8,310,312; 8,315,970; 8,331,511; 8,331,879; 8,345,348; 8,346,692; 8,346,693; 8,346,711; 8,346,712; 8,351,876; 8,354,884; 8,355,684; 8,358,169; 8,364,095; 8,369,447; 8,369,595; 8,380,773; 8,390,375; 8,390,376; 8,396,693; 8,410,843; 8,410,850; 8,412,133; 8,421,534; 8,432,220; 8,437,513; 8,463,582; 8,467,438; 8,477,581; 8,483,343; 8,483,450; 8,487,706; 8,489,047; 8,494,463; 8,498,369; 8,509,347; 8,509,712; 8,519,440; 8,532,215; 8,532,964; 8,538,039; 8,564,368; 8,565,343; 8,577,311; 8,587,375; 8,599,050; 8,605,814; 8,605,819; 8,611,190; 8,611,459; 8,611,820; 8,615,208; 8,619,905; 8,620,631; 8,626,089; 8,649,743; 8,675,925; 8,704,595; 8,705,166; 8,712,345; 8,718,178; 8,718,209; 8,724,857; 8,737,937; 8,737,938; 8,744,141; 8,744,377; 8,758,271; 8,761,409; 8,766,917; 8,767,869; 8,780,693; 8,787,628; 8,798,559; 8,804,807; 8,804,871; 8,811,532; 8,823,452; 8,831,074; 8,831,133; 8,831,135; 8,838,218; 8,843,088; 8,843,089; 8,849,611; 8,855,175; 8,855,234; 8,867,601; 8,874,411; 8,885,765; 8,886,341; 8,891,701; 8,896,471; 8,897,351; 8,903,192; 8,909,176; 8,909,328; 8,933,752; 8,934,573; 8,958,470; 8,964,901; 8,964,996; 8,971,834; 8,976,896; 8,994,657; 8,995,571; 8,995,835; 9,008,153; 9,014,299; 9,019,643; 9,020,454; 9,025,607; 9,031,168; 9,036,734; 9,048,865; 9,048,900; 9,071,313; 9,077,508; 9,088,472; 9,094,036; 9,094,151; 9,104,921; 9,106,304; 9,130,628; 9,137,492; 9,143,274; 9,160,280; 9,160,310; 9,160,687; 9,166,610; 9,166,635; 9,166,698; 9,171,534; 9,184,784; 9,185,529; 9,189,458; 9,191,041; 9,191,049; 9,199,860; 9,209,753; 9,209,841; 9,214,968; 9,214,969; 9,225,295; 9,225,501; 9,231,530; 9,231,647; 9,231,801; 9,236,996; 9,246,525; 9,246,731; 9,252,798; 9,252,821; 9,253,608; 9,257,943; 9,258,156; 9,261,978; 9,264,153; 9,265,461; 9,270,304; 9,270,512; 9,271,123; 9,276,602; 9,294,113; 9,304,501; 9,306,606; 9,311,535; 9,312,892; 9,314,623; 9,322,906; 9,337,781; 9,337,783; 9,352,155; 9,361,681; 9,361,936; 9,362,869; 9,362,942; 9,363,068; 9,369,093; 9,369,255; 9,369,541; 9,397,516; 9,404,950; 9,413,516; 9,419,722; 9,431,972; 9,438,178; 9,438,356; 9,439,597; 9,451,920; 9,460,246; 9,461,597; 9,461,676; 9,473,077; 9,479,322; 9,509,331; 9,509,350; 9,517,030; 9,531,475; 9,536,539; 9,537,759; 9,544,126; 9,559,831; 9,564,876; 9,571,312; 9,575,570; 9,590,664; 9,590,668; 9,595,920; 9,595,982; 9,607,003; 9,607,628; 9,608,676; 9,608,718; 9,614,554; 9,628,119; 9,628,120; 9,646,116; 9,647,717; 9,654,211; 9,654,216; 9,659,120; 9,660,593; 9,660,730; 9,665,510; 9,667,292; 9,674,368; 9,680,423; 9,680,497; 9,697,845; 9,705,477; 9,706,296; 9,712,179; 9,712,233; 9,713,010; 9,722,646; 9,722,691; 9,726,701; 9,727,677; 9,735,741; 9,735,800; 9,735,811; 9,735,876; 9,737,258; 9,742,599; 9,746,506; 9,749,161; 9,755,691; 9,762268; 9,768,891; 9,778,902; 9,780,869; 9,780,881; 9,787,459; 9,794,000; 9,800,437; 9,800,734; 9,820311; 9,831,899; 9,837,970; 9,843,346; 9,859,845; 9,866,183; 9,877,265; 9,882,648; 9,887,862; 9,900088; 9,912,435; 9,913,194; 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