An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (NCEM). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts.

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar portion. The stacked body includes a first insulating layer provided on the substrate, a first electrode layer provided on the first insulating layer and including polycrystalline silicon, a second insulating layer provided on the first electrode layer, and a second electrode layer provided on the second insulating layer. The columnar portion includes a semiconductor layer extending in a stacking direction of the stacked body and a memory layer provided between the semiconductor layer and the stacked body. The first and second electrode layers respectively have a first thickness and a second thickness in the stacking direction, and the first thickness of the first electrode layer is thicker than the second thickness of the second electrode layer.

The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.

Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.

A volatile memory array using vertical thyristors is disclosed together with methods of fabricating the array.

A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.

Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of the set of fins has respective cut faces located at the fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends on the set of fins of the FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.

An eFuse device on a substrate is formed on a substrate used for an integrated circuit. A semiconductor structure is created from a semiconductor layer deposited over the substrate. A mask layer is patterned over the semiconductor structure such that a first region of the semiconductor structure is exposed and a second region of the semiconductor structure is protected by the mask layer. Next, a self-limiting etch is performed on the exposed areas in the first region of the semiconductor structure, producing a first faceted region of the semiconductor structure in the first region. The semiconductor in the first faceted region has a minimum, nonzero thickness at a point where two semiconductor facet planes meet which is thinner than a thickness of semiconductor in the second region of the semiconductor structure is protected by the mask layer. The first faceted region is used as a link structure in the eFuse device.

A system includes at least one Input/Output (I/O) interface and a processor. The processor is coupled to the at least one I/O interface. The processor is configured to perform, according to a file or a rule inputted from the at least one I/O interface, operations below. When the at least one condition is present in a signal to be received or transmitted by a terminal of a cell, a plurality of conductive segments is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. When the at least one condition one is not present in the signal, a single route is assigned to the terminal of the cell, to transmit the signal to the terminal of the cell. The single route and each of the conductive segments are configured to have the same width.