Embodiments relate to MEMS devices and methods for manufacturing MEMS devices. In one embodiment, the manufacturing includes forming a monocrystalline sacrificial layer on a non-silicon-on-insulator (non-SOI) substrate, patterning the monocrystalline sacrificial layer such that the monocrystalline sacrificial layer remains in a first portion and is removed in a second portion lateral to the first portion; depositing a first silicon layer, the first silicon layer deposited on the remaining monocrystalline sacrificial layer and further lateral to the first portion; removing at least a portion of the monocrystalline sacrificial layer via at least one release aperture in the first silicon layer to form a cavity and sealing the cavity.

Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.

A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

A pseudo resistance circuit includes a first gate voltage adjustment circuit that adjusts respective currents of first and second current sources and also adjusts a gate voltage of a second field effect transistor to equalize or substantially equalize a drain voltage of the second field effect transistor and a voltage of a first end portion of a reference resistance element and controls a drain voltage of a first field effect transistor and the drain voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other; and a second gate voltage adjustment circuit that adjusts a gate voltage of the first field effect transistor to control the gate voltage of the second field effect transistor and the gate voltage of the first field effect transistor to maintain a constant or substantially constant relationship with each other.

A drive circuit includes: a constant current circuit configured to supply a constant current to a gate of the voltage-controlled device, and to turn on the voltage-controlled device; a discharge circuit configured to supply a discharge current between the gate and an emitter of the voltage-controlled device, and to turn off the voltage-controlled device; a switch circuit configured to operate one of the constant current circuit or the discharge circuit depending on a drive signal, and to turn on or turn off the voltage-controlled device; a current instruction value generation circuit configured to generate and output at least a current instruction value that sets an output current from the constant current circuit; and a current control circuit configured to control the output current from the constant current circuit based on the current instruction value generated by the current instruction value generation circuit.

It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

A thin-film integrated circuit comprising a first semiconductor device, a second semiconductor device, a first resistor, and a second resistor is provided. A semiconducting region of the first semiconductor device, a resistor body of the first resistor, a semiconducting region of the second semiconductor device, and a resistor body of the second resistor are formed from at least one of a first source material and a second source material, and a material of the resistor body of the first resistor and a material of the resistor body of the second resistor have different electrical properties.

The safety is ensured in such a manner that an abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early and a warning is given to a user. A first protection circuit and a second protection circuit are provided for one secondary battery. The first protection circuit includes a memory circuit including a transistor including an oxide semiconductor. Combination of a plurality of protection circuits enables a complementary double protection system in charging, and the safety can be further enhanced.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, and a memory cell including a transistor and a capacitor. The transistor includes an oxide over the first insulator, a first conductor and a second conductor over the oxide, a third insulator over the oxide, and a third conductor over the third insulator. The third insulator and the third conductor are located in a first opening of the second insulator. The capacitor includes a fourth conductor in contact with a top surface of the second conductor, a fourth insulator over the fourth conductor, and a fifth conductor over the fourth insulator. The fourth conductor, the fourth insulator, and the fifth conductor are located in a second opening of the second insulator. A third opening is formed in the first insulator, the second insulator, and the first conductor. A sixth conductor is located in the third opening. The sixth conductor includes a region in contact with part of a top surface of the first conductor and part of a side surface of the first conductor in each of a plurality of layers.