A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

A gate structure includes a gate portion and a field plate portion, a projection of a tail end point on a lower surface of the lower field plate sub-portion is located on a side, close to the first plane, of a projection of a start end point on a lower surface of an upper field plate sub-portion, and the start end point on the lower surface of the upper field plate sub-portion is coincidence with an end point where an upper surface of the lower field plate sub-portion is connected to the lower surface of the upper field plate sub-portion. In the gate structure of the present disclosure, the two adjacent field plate sub-portions are non-perpendicularly connected to each other, thereby achieving an effect of optimizing electric field distribution, thus improving reliability and stability of semiconductor devices.

An apparatus includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a conductive metallic region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer. Additionally, the conductive metallic region is structured and arranged to extend a limited length parallel to said group III-Nitride barrier layer.

The present disclosure relates to a transistor device. The transistor device includes a plurality of source contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate. The plurality of gate structures wrap around one or more of the plurality of source contacts in one or more closed loops. A drain contact is disposed over the substrate. The drain contact continuously wraps around one or more of the plurality of gate structures as a continuous structure. The plurality of gate structures are separated from the drain contact by a first distance and are separated from a source contact of the plurality of source contacts by a second distance. The second distance is different than the first distance.

The present disclosure relates to the formation of a variable trench dimension area, including a plurality of trenches extending in a strip-like fashion in top-plan view. A bigger trench hosts both the source poly field plate contact and the poly gate region. All of the trenches are spaced apart from one another by a constant quantity, to maintain the expected field plate effect and avoid impact on breakdown voltage. To recover the resulting bigger pitch dimension, the trenches around the bigger one are formed with smaller and decreasing dimension from the inner to the outer one. The sum of the pitch of these cells will result equivalent to the sum of the pitch of the same numbers of standard cells. In this way the impact on electrical performances and efficiency is limited or even avoided.

In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.

The invention provides a laterally diffused metal-oxide-semiconductor (LDMOS), which comprises a substrate, a plurality of fin structures on the substrate, a gate structure on the substrate and spanning the fin structures, and a gate contact layer on the gate structure, wherein the gate contact layer is electrically connected with a dummy contact structure.

An integrated circuit includes a doping region extending in a first direction, the doping region being doped with a first-type dopant; a gate structure at least partially overlapping the doping region; a drain contact region in the doping region and spaced apart from the gate structure in the first direction, the drain contact region being doped with the first-type dopant at a higher concentration than the doping region; a dielectric layer on the doping region between the gate structure and the drain contact region; a first contact electrically connected to the dielectric layer; and a second contact electrically connected to the drain contact region and electrically connected to the first contact.

Lateral III-N devices such as AlGaN/GaN HEMTs can have structures which serve to improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure that includes a III-N buffer layer, a III-N channel layer and a III-N barrier layer where a compositional difference induces a 2DEG channel therein. The first portion is in ohmic contact with the 2DEG channel and the second portion extends over a top surface of the III-N barrier layer and is in direct contact with the top surface of the III-N barrier layer. The device further includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage which is greater than the drain-to-substrate pinch-off voltage, and the 2DEG channel is fully depleted of charge below the second portion of the drain electrode when the III-N device is biased at or above the maximum rated drain-to-source operating voltage.