An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor device according to the present invention is a semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate, the semiconductor device including an electrode pad which is arranged avoiding the transistor cell region on the semiconductor substrate and is electrically connected to a one-side current electrode of each of the cells, in which the transistor cell region contains a plurality of regions each of which has a different current drive capability from each other depending on a distance from the electrode pad.

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.

An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG semiconductor structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure on the silicon.

A semiconductor device has a deep trench in a semiconductor substrate of the semiconductor device, with linear trench segments extending to a trench intersection. Adjacent linear trench segments are connected by connector trench segments that surround a substrate pillar in the trench intersection. Each connector trench segment has a width at least as great as widths of the linear trench segments connected by the connector trench segment. The deep trench includes a trench filler material. The deep trench may have three linear trench segments extending to the trench intersection, connected by three connector trench segments, or may have four linear trench segments extending to the trench intersection, connected by four connector trench segments.

According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.