A resistive switching memory device using a brownmillerite-structured material, the resistive switching memory device comprises a first electrode comprising an oxide electrode; a resistive switching unit that is disposed on the first electrode and comprises a thin-film of a brownmillerite structured oxide; and a second electrode that is disposed on the resistive switching unit. Furthermore, the resistive switching unit has a structure in which an octahedron structure layer and a tetrahedron structure layer are sequentially stacked.

A power module and a manufacturing method thereof are provided, and the power module includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding substrate, a top interconnection layer and a lead frame. The interconnection layer is disposed on the carrier substrate. The first chip and the second chip are disposed on the interconnection layer, and electrically connected to the interconnection layer. The ceramic bonding substrate is disposed on the interconnection layer, and is disposed in between the first chip and the second chip so as to separate the first chip from the second chip. The top interconnection layer is disposed on the ceramic bonding substrate, covers the first chip and the second chip, and is electrically connected to the first chip and the second chip. The lead frame is disposed on the top interconnection layer and electrically connected to the top interconnection layer.

Various systems, devices, articles and methods related to one or more local luminescent defects disposed within semiconductor body including silicon. A respective defect included in the one or more defects supports a respective bound exciton. A respective pair of computational states is defined at the respective defect and one computational state of the pair of computational states includes a first configuration for the respective exciton. Information stored in the respective pair of computational states can be manipulated according to various systems, devices, articles and methods described herein.

A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.

A population of nanowires can be prepared by a method involving electric field catalyzed growth and alteration based on surface charge density.

A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.

A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.