A semiconductor device includes a gate structure on a substrate, a spacer around the gate structure, and a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

There is provided a method for forming a semiconductor device. The method comprising performing frontside processing comprising forming a transistor structure on a frontside of a substrate, the transistor structure comprising a first source/drain body and a second source/drain body located in a first and a second source/drain region, respectively, and a channel structure between the first source/drain body and the second source/drain body, wherein the first source/drain body and the second source/drain body have a first doping concentration. The method also includes, subsequent to the frontside processing, performing backside processing comprising exposing the first source/drain body from a backside of the substrate, and processing the first source/drain body to form, in the first source/drain region, a replacement source/drain body having a second doping concentration different from the first doping concentration.

A semiconductor device includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type; a fifth semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration lower than an impurity concentration of the second semiconductor layer; a first electrode; and a second electrode. The fifth semiconductor region has one surface in contact with the first semiconductor region, another surface in contact with the third semiconductor region, and a side surface in contact with the gate insulating film.

A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.

A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.

A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.

Provided is a nitride semiconductor device including a p-type region having a high effective acceptor concentration while exhibiting good electrical characteristics, and a method of manufacturing the same. The nitride semiconductor device includes: a nitride semiconductor; and a p-type region provided in the nitride semiconductor. The p-type region includes an acceptor element and entirely has a concentration in a range of 510.sup.18 cm.sup.3 or higher and 110.sup.21 cm.sup.3 or lower. The p-type region includes a segregation part in which the acceptor element is partly segregated, and a matrix in which the acceptor element is not segregated. The concentration of the acceptor element in the segregation part is 4.6 times or smaller as high as that in the matrix.