The present disclosure provides a semiconductor device, including a substrate, a first active region in the substrate, a second active region in the substrate and adjacent to the first active region, an isolation region in the substrate and between the first active region and the second active region, and a dummy gate overlapping with the isolation region, wherein an entire bottom width of the dummy gate is greater than an entire top width of the isolation region.

Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.

Addressable actuator and arrays thereof are described. Actuators may be dielectric elastomer actuators (DBAs). An addressable actuator may include a compliant substrate, with an optical receiver integrated with a first region of the compliant substrate and an actuator integrated with a second region of the compliant substrate, with the optical receiver coupled to the actuator. The optical receivers may comprise percolating networks of semiconductor materials, such as photoconductive channels of zinc oxide nanowires, which may be embedded in a compliant substate, or one or more compliant layers (which may be formed on a substrate). Compliant substrates or layers may include complaint materials such as an elastomer. An actuator array may comprise multiple of the actuators, with each actuator being independently optically addressable. A system may include light emitting devices optically coupled to respective optical receivers to control actuation of the actuators using light.

A semiconductor device includes a first cobalt-containing plug disposed over a substrate, a second cobalt-containing plug disposed over the first cobalt-containing plug, a first barrier layer over sidewalls of the second cobalt-containing plug, a second barrier layer over sidewalls of the first barrier layer, and a dielectric layer surrounding the second barrier layer. The first barrier layer contains a metal element. The first and second barrier layers include different material compositions.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a semiconductor fin and a gate stack wrapped around the channel structures. The semiconductor device structure also includes a source/drain epitaxial structure adjacent to the channel structures and an isolation structure surrounding the semiconductor fin. A protruding portion of the semiconductor fin protrudes from a top surface of the isolation structure. The semiconductor device structure further includes an embedded epitaxial structure adjacent to a first side surface of the protruding portion of the semiconductor fin.

A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height.

A method includes forming a structure having a dummy gate stack over a fin protruding from a substrate. The fin includes an ML of alternating semiconductor layers and sacrificial layers. The method further includes forming a recess in an S/D region of the ML, forming a recess of the ML, and forming inner spacers on sidewalls of the sacrificial layers. Each inner spacer includes a first layer embedded in the sacrificial layer and a second layer over the first layer. The method further includes forming an S/D feature in the recess, such that the second layer of the inner spacers is embedded in the S/D feature. The method further includes removing the dummy gate stack to form a gate trench, removing the sacrificial layers from the ML, thereby forming openings interleaved between the semiconductor layers, and subsequently forming a high-k metal gate stack in the gate trench and the openings.

Provided is a semiconductor apparatus comprising: a semiconductor substrate; an element electrode provided above the semiconductor substrate; an element electrode pad electrically connected to the element electrode; and a wire configured to connect to the element electrode pad at a plurality of connection points, wherein the semiconductor substrate includes an emitter region of a first conductivity type arrayed in an array direction, the emitter region facing the element electrode on an upper surface of the semiconductor substrate, wherein a density of the emitter region below a connection point of any of the wires is different from a density of the emitter region below a connection point of any other of the wires.

A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

A method of manufacturing an integrated circuit (IC) includes providing a structure having a fin over a substrate in a region of the IC, a sacrificial gate stack engaging a channel region of the fin, and gate spacers on sidewalls of the sacrificial gate stack. The first layers and the second layers are alternately stacked over the substrate. The method also includes etching the fin adjacent the gate spacers, resulting in source/drain trenches, partially recessing the second layers exposed in the source/drain trenches, resulting in gaps between adjacent layers of the first layers in the fin, depositing inner spacer features in the gaps in the fin, epitaxially growing source/drain features in the source/drain trenches, and replacing the sacrificial gate stack with a metal gate stack. The metal gate stack includes a gate dielectric layer disposed over top and sidewalls of the fin having both the first and the second layers.