A variable transmission display comprises an electrophoretic medium having electrically charged particles dispersed in a fluid, the electrophoretic medium being capable of assuming a light-transmissive state and a substantially non-light-transmissive state; a light-transmissive first electrode disposed adjacent one side of the electrophoretic medium; light-transmissive second electrodes disposed adjacent the other side of the electrophoretic medium; and voltage means for varying the potential each of the second electrodes independently of one another.

An object of the present invention is to provide a light emitting device in which variations in an emission spectrum depending on a viewing angle with respect to a side from which luminescence is extracted are decreased. A light emitting device according to the invention has a transistor, an insulating layer covering the transistor and a light emitting element provided in an opening of the insulating layer. The transistor and the light emitting element are electronically connected through a connecting portion. Additionally, the connecting portion is connected to the transistor through a contact hole penetrating the insulating layer. Note that the insulating layer may be a single layer or a multilayer in which a plurality of layers including different substances is laminated.

A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

A display panel including pixels disposed on a substrate, where each of the pixels includes a light emitting element, and a capacitor. The capacitor of a first one of the pixels is partially overlapped, in a vertical direction, by respective pixel areas of two of the pixels. The anode of the capacitor of the first one of the pixels may be disposed closer to the substrate than a cathode of the capacitor, thereby reducing a parasitic capacitance between the capacitor and an anode of the light emitting element of one of the two pixels overlapping the capacitor.

A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Embodiments of this disclosure dislcose a display panel and a manufacturing method thereof, as well as a display device. The display panel comprises an upper substrate and a lower substrate arranged opposite to each other and packaged together, and further comprises an electrically controlled deformable film arranged on a surface of the upper substrate facing away from the lower substrate. The electrically controlled deformable film is configured to adjust its curvature based on a voltage applied on the electrically controlled deformable film, and enable a curvature of the upper substrate and a curvature of the lower substrate to be adjusted synchronously.

Embodiments of the disclosure provide an array substrate, a method of manufacturing an array substrate, a liquid crystal display panel, and a display device. The array substrate comprises: a common electrode and a pixel electrode on a base substrate; and a passivation layer between the common electrode and the pixel electrode. The pixel electrode is a grating structure comprising a plurality of sub-pixel electrodes. The sub-pixel electrode comprises a body structure extending in a first direction, and a bending structure extending in a second direction and formed at an end portion of at least one end of the body structure. A protrusion is disposed at a joint of the body structure and the bending structure.

A TFT substrate and a method for manufacturing the TFT substrate are provided. A TFT structure is formed on a substrate. A color resist layer is formed on the substrate, and a first opening area is formed in the color resist layer at a location corresponding to the TFT structure. A first black matrix is formed in the first opening area such that the TFT structure is covered by the first black matrix. A pixel electrode is formed on the color resist layer and the first black matrix and is electrically coupled to the TFT structure through the first black matrix. With such an arrangement, light can be shielded and light transmittance can be reduced when a panel including the TFT substrate is bent. This helps improve contrast of the panel.