A silicon-based quantum device for confining charge carriers is provided. The device comprises: a substrate having a first planar region 137; a silicon layer 32 which forms part of the substrate and includes a step 33 with an edge 34 and a second planar region 135, wherein the second planar region 135 is substantially parallel to and offset from the first planar region 137; a first electrically insulating layer 42 provided on the silicon layer 32, overlying the step 33; a first metallic layer 51, provided on the first electrically insulating layer 42, overlying the step 33, arranged to be electrically connected such that a first confinement region 10 can be induced in which a charge carrier or charge carriers can be confined at the edge 34; and a second metallic layer 52, provided overlying the second planar region 135 of the silicon layer, wherein the second metallic layer is: electrically separated from the first metallic layer 51; and arranged to be electrically connected such that a second confinement region 11 can be induced in which a charge carrier or charge carriers can be confined only in the second planar region 135 of the silicon layer 32 under the second metallic layer 52, and the first confinement region 10 is couplable to the second confinement region 11; wherein the first confinement region 10 is displaced from the second confinement region 11 in a direction that is perpendicular to the edge 34. A method of assembling a silicon-based quantum device and a method of using a silicon-based quantum device are also provided.

A method includes following steps. A channel region is formed extending lengthwise along a first direction over a substrate. Source/drain features are formed interfacing opposite sidewalls of the channel region, respectively. An MTJ-containing gate structure is formed extending lengthwise along a second direction across the channel region. The MTJ-containing gate structure comprises a gate dielectric layer over the channel region, an MTJ stack over the gate dielectric layer, and a gate metal over the MTJ stack. In a write operation of the MTJ stack, a capacitance of the MTJ stack is switched by controlling a voltage pulse duration of a gate voltage applied across the MTJ stack, with no current flowing through the MTJ stack in the write operation for writing the MTJ stack.

The disclosure describes an adaptive and optimal imaging of individual quantum emitters within a lattice or optical field of view for quantum computing. Advanced image processing techniques are described to identify individual optically active quantum bits (qubits) with an imager. Images of individual and optically-resolved quantum emitters fluorescing as a lattice are decomposed and recognized based on fluorescence. Expected spatial distributions of the quantum emitters guides the processing, which uses adaptive fitting of peak distribution functions to determine the number of quantum emitters in real time. These techniques can be used for the loading process, where atoms or ions enter the trap one-by-one, for the identification of solid-state emitters, and for internal state-detection of the quantum emitters, where each emitter can be fluorescent or dark depending on its internal state. This latter application is relevant to efficient and fast detection of optically active qubits in quantum simulations and quantum computing.

A semiconductor tunnel FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source/drain region and a second source/drain region. The first source/drain region includes a p-type material; and the second source/drain region includes an n-type material.

Disclosed are embodiments of a trancitor semiconductor device having a channel made of a ferromagnetic, ferrimagnetic or antiferromagnetic material, wherein the channel is interposed between a source, a drain, and a dielectric material adjacent to the channel. Two tap terminals adjacent to the dielectric material measure a voltage produced by an anomalous Hall effect (AHE) when current flows from the source to the drain. In an embodiment, a gate is provided that can modulate the conductivity of the channel. In an embodiment, no gate is provided and the extent of the voltage induced by the AHE is controlled only by a current applied at the source terminal. Planar and three-dimensional embodiments are also disclosed.

A quantum information processing device including a semiconductor substrate. An optical resonator is coupled to the substrate. The optical resonator supports a first photonic mode with a first resonator frequency. The quantum information processing device includes a non-gaseous chalcogen donor atom disposed within the semiconductor substrate and optically coupled to the optical resonator. The donor atom has a transition frequency in resonance with the resonator frequency. Also disclosed herein are systems, devices, articles and methods with practical application in quantum information processing including or associated with one or more deep impurities in a silicon substrate optically coupled to an optical structure.

A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.

A device for shielding at least one component from thermal radiation, the device comprising at least a first substrate with a first surface and a second surface and a second substrate with a first surface and second surface, the first surface of the second substrate being arranged to at least partially face the second surface of the first substrate. The device additionally comprises at least a first component arranged on the first surface of the second substrate or the second surface of the first substrate and a shielding arrangement comprising a plurality of shielding elements comprising electrically conductive material, the shielding elements being configured to essentially surround at least the first component to provide a shielded area within which the first component is located, wherein electromagnetic radiation having wavelength longer than a selected first wavelength is essentially prevented from reaching the shielded area.

An array of gate structures is produced on a planar surface, the array being suitable for the production of a spin qubit quantum dot device. The gate structures include alternately arranged structures of a first and second type. According to the example embodiments, electrical connections to the gate structures of the first and second type are produced in separate process step sequences. The connections to the first gate type include the formation of first conductive lines running essentially parallel to the planar surface and connected to the gate structures of the first type by first via connections. Before producing similar connections to the gate structures of the second type, a conformal dielectric layer is formed on the first conductive lines. The conformal layer is configured so that it forms a protective spacer on the sidewalls of the first conductive lines during processing of the second conductive lines, to avoid shorting.

A system for quantum information processing (1) is described which includes a body of material (2) having first and second opposite faces (3, 4) and at least one two-dimensional array (7) of defects (5.sub.i,k, 5.sub.i+1,k, 5.sub.i,k+1 . . . 5.sub.n,m) embedded in the body of material at a depth (d.sub.1) of between 0.2 m and 6 m from the first face.