An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.

The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels in pixel areas defined by the gate lines and the data lines. Dimensions of the sub-pixels are identical. Each sub-pixel is in a color different from an adjacent sub-pixel. A quadrate pixel unit is defined by at most two adjacent sub-pixels in each row of sub-pixels, and two adjacent rows of sub-pixels are staggered by sub-pixel in a column direction. The data lines include first data lines. Each of the first data lines is in an interval between a column of sub-pixels and an adjacent column of sub-pixels and is connected with sub-pixels of the two columns.

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.

An integrated circuit has a set of circuit components. The set of circuit components enables the circuit to execute an action. The integrated circuit has a structural weakness. In response to undergoing a mechanical force, the structural weakness will cause the integrated circuit to undergo a structural failure. A human is able to provide the mechanical force without the use of tools. The structural failure will alter one or more circuit components of the set of circuit components. The alteration will result in the set of circuit components no longer enabling the integrated circuit to execute the action.

A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.

This disclosure is directed to devices, integrated circuits, and methods for sensing radiation. In one example, a device includes an oscillator, configured to deliver a signal via an output at intervals defined by an oscillation frequency, and a counter, connected to the output of the oscillator and configured to count a number of times the comparator delivers the output signal. The oscillator includes a radiation-sensitive cell that applies a resistance. The resistance of the radiation-sensitive cell is configured to vary in response to incident radiation, wherein the oscillation frequency varies based at least in part on the resistance of the radiation-sensitive cell.

Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.