A thin film transistor and a fabrication method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a gate electrode (2), a source electrode (5) and a drain electrode (6) disposed in a same layer on a base substrate (1); a gate insulating layer (3) disposed on the gate electrode (2), the source electrode (5) and the drain electrode (6); an active layer (4) disposed on the gate insulating layer (3); a passivation layer (7) disposed on the active layer (4) and the gate insulating layer (3). A first via hole (81) and a second via hole (91) are disposed in the passivation layer (7); a third via hole (82) and a fourth via hole (92) are disposed in the passivation layer (7) and the gate insulating layer (3); a first connection pattern (8) and a second connection pattern (9) are disposed on the passivation layer (7); the first connection pattern (8) is connected with the active layer (4) and the source electrode (5) through the first via hole (81) and the third via hole (82) respectively; the second connection pattern (9) is connected with the active layer (4) and the drain electrode (6) through the second via hole (91) and the fourth via hole (92) respectively. The thin film transistor effectively reduces the influence of the parasitic capacitance between the source electrode and the gate electrode and the parasitic capacitance between the drain electrode and the gate electrode on the thin film transistor.

A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.

A processing method for processing a single-crystal silicon wafer that has a first surface and a second surface formed in such a manner that a specific crystal plane included in a crystal plane {100} is exposed in each of the first and second surfaces and has devices formed in the respective regions marked out by planned dividing lines in the first surface. The method includes forming dividing origins along each planned dividing line, forming a separation layer along the crystal plane of the second surface through relatively moving a focal point and the wafer along a first direction that is parallel to the crystal plane of the second surface and in which an acute angle formed between the first direction and the crystal orientation <100> is equal to or smaller than 5, and separating the wafer into a first-surface-side wafer including devices and a second-surface-side wafer including no devices.

A manufacturing method for a semiconductor chip includes: preparing a GaN wafer; producing a processed wafer by forming an epitaxial film on a surface of the GaN wafer to have chip formation regions adjacent to a first surface of the processed wafer; forming a first surface-side element component of a semiconductor element in each chip formation region; forming a wafer transformation layer along a planar direction of the processed wafer by irradiating an inside of the processed wafer with a laser beam; dividing the processed wafer at the wafer transformation layer into a chip formation wafer and a recycle wafer; extracting a semiconductor chip from the chip formation wafer; and after the preparing the GaN wafer and before the dividing the processed wafer, irradiating an inside of the gallium nitride wafer or the processed wafer with a laser beam to form a mark by deposition of gallium.

An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.

A substrate dividing method includes preparing a substrate that is formed with division start points along streets and that has a protective sheet attached to a surface on one side thereof and rolling a roller on a surface on the other side of the substrate, to attach an expanding tape. Next, suction by a holding table is cancelled, and, in a state in which a slight gap is formed between a holding surface of the holding table and the protective sheet, the roller is brought into contact with the expanding tape and rolled, thereby extending cracks extending from the division start points while causing the substrate to sink into the gap through the protective sheet with the division start points as starting points, and the expanding tape is expanded to widen the chip intervals with the division start points as starting points.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.