Provided is a semiconductor device including a semiconductor substrate, a plurality of gate electrodes disposed on the upper surface portion of the semiconductor substrate and spaced apart from each other, a plurality of emitter electrodes disposed to be overlapped with each of the plurality of gate electrodes, and a collector electrode disposed on the lower surface of the semiconductor substrate.

Provided is a semiconductor device that includes a drift region that is of a first conductivity type and is provided in a semiconductor substrate; a base region that is of a second conductivity type and is provided above the drift region; an accumulation region that is of the first conductivity type provided between the base region and the drift region; and an electric field relaxation region that is provided between the base region and the accumulation region, wherein the boundary between the electric field relaxation region and the accumulation region is a location for a half-value for the peak of the doping concentration of the accumulation region, and an integrated concentration of the electric field relaxation region is greater than or equal to 5E14 cm.sup.2 and less than or equal to 5E15 cm.sup.2.

A semiconductor device includes: a first electrode; a first semiconductor layer on the first electrode in a diode region; a second semiconductor layer on the first electrode in an IGBT region; a semiconductor layer on the first and second semiconductor layers, a first upper layer of the semiconductor layer in the diode region including a first region adjacent to the IGBT region and a second region separated from the IGBT region, an impurity concentration being less in the first region than in the second region; a third semiconductor layer on the semiconductor layer; a fourth semiconductor layer of the third semiconductor layer in the IGBT region; a third electrode extending in a direction from the fourth semiconductor layer toward the semiconductor layer; and an insulating film between the second electrode and each of the third semiconductor layer, the semiconductor layer, and the third electrode.

A semiconductor device includes: a drift region of a first conductivity type in a semiconductor body having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; and trenches extending into the semiconductor body from the first main surface and patterning the semiconductor body into mesas. The trenches include: a first trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; a second trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes; and a third trench having first and second electrodes that face one another along a lateral direction, and a dielectric arranged between the first and second electrodes. Additional semiconductor device embodiments are described herein.

In a vertical power device with trenched insulated gates, there is an npnp layered structure. The vertical gates turn on the device with a suitable gate bias to conduct a current between a top electrode and a bottom electrode. In an example, implanted n+ source regions are formed in the top surface within a p-well. Between some gates, the overlying dielectric is opened up, by etching, to expose distributed p-type contact regions for the p-well. The dielectric is also opened up to expose areas of the n+ source regions. The top electrode metal directly contacts the exposed p-type contact regions and the n+ source regions to provide distributed emitter-to-base short across the cellular array to improve device performance in the presence of transients. The p-contact regions are isolated from the n+ source regions, prior to the deposition of the metal electrode, due to the p-type contact regions not abutting the n+ source regions.

The present invention can reduce an on-resistance while suppressing reduction in a short circuit capacity. The present invention includes a SiC epitaxial layer, a well region, a source region, a channel resistance adjusting region, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The channel resistance adjusting region is sandwiched between the source region and the SiC epitaxial layer in a surface layer of the well region. The channel resistance adjusting region is a region in which a first impurity region is intermittently formed in a direction intersecting a direction in which the source region and the SiC epitaxial layer sandwich the channel resistance adjusting region.

An SJ-MOSFET and IGBT are provided in a single semiconductor chip. Furthermore, a balance is made between a carrier amount of n-type columns and a carrier amount of p-type columns, to encourage formation of a depletion layer in when a reverse voltage is applied in the SJ-MOSFET section. Provided is a includes a semiconductor substrate, a super junction structure formed on a front surface side of the semiconductor substrate, and a field stop layer formed at a position overlapping with the super junction structure on a back surface side of the semiconductor substrate, in a manner to not contact an end of the super junction structure on the back surface side.

A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of gate electrodes formed in the trenches, a base region and an anode region formed between adjacent trenches respectively in first and second element regions of the semiconductor substrate, a plurality of emitter regions and contact regions selectively formed in the base region, an interlayer insulating film covering the gate electrodes, first and second contact holes penetrating the interlayer insulating film, a plurality of contact plugs embedded in the first contact holes, a first electrode contacting the contact plugs and contacting the anode region via the second contact hole, a collector region and a cathode region formed on a back surface of the semiconductor substrate respectively in the first and second element regions, and a second electrode contacting the collector region and the cathode region.

A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.

A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in the surface portion of the semiconductor layer with each body region forming a unit cell, a source region of the first conductivity type formed in the inner portion of the body region, a gate electrode facing the body region across a gate insulating film, a drain region of the first conductivity type and a collector region of the second conductivity type formed in the rear surface portion of the semiconductor layer such that the drain region and the collector region adjoin each other, and a drift region between the body region and the drain region, wherein the collector region is formed such that the collector region covers a region including at least two unit cells in the x-axis direction along the surface of the semiconductor layer.