Methods and systems for hybrid integration of optical communication systems are disclosed and may include receiving continuous wave (CW) optical signals in a silicon photonics die (SPD) from an optical source external to the SPD. The received CW optical signals may be processed based on electrical signals received from an electronics die bonded to the SPD via metal interconnects. Modulated optical signals may be received in the SPD from optical fibers coupled to the SPD. Electrical signals may be generated in the SPD based on the received modulated optical signals and communicated to the electronics die via the metal interconnects. The CW optical signals may be received from an optical source assembly coupled to the SPD and/or from one or more optical fibers coupled to the SPD. The received CW optical signals may be processed utilizing one or more optical modulators, which may comprise Mach-Zehnder interferometer modulators.

A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a first gate electrode over a substrate while heated at a temperature higher than or equal to 450 C. and lower than the strain point of the substrate, forming a first oxide semiconductor film over the first insulating film, adding oxygen to the first oxide semiconductor film and then forming a second oxide semiconductor film over the first oxide semiconductor film, and performing heat treatment so that part of oxygen contained in the first oxide semiconductor film is transferred to the second oxide semiconductor film.

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

To provide a semiconductor device including element layers that are stacked. A first wiring layer and a second wiring layer are stacked between a first element layer and a second element layer. A third wiring layer and a fourth wiring layer are stacked over the second element layer. Transistors of logic cells are provided in the first element layer. Wirings of the logic cells are provided in the first wiring layer or the second wiring layer. Input ports and output ports of the logic cells are provided in the third wiring layer. The input port of one of the logic cells is connected to the output port of another logic cell through the wiring of the third wiring layer or the fourth wiring layer. Connecting the logic cells through the wiring layers over the second element layer improves the efficiency of steps of arranging and connecting the logic cells.

Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as a capacitor and a resistor structure, in a substrate, wherein the passive structures are vertically disposed within the substrate. An insulator layer is formed on a top surface of the passive structure, a device layer is formed on the insulator layer, and a contact is formed to couple a device disposed in the device layer to the at least one passive structure.

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage. In addition, a transistor (for example, a silicon transistor or the like) capable of higher operation than a transistor including an oxide semiconductor is preferably used as a transistor in a circuit (specifically, for example, a buffer circuit, a flip-flop circuit, or the like) requiring a lower withstand voltage than the level shift circuit.

Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.