A method of manufacturing a silicon carbide device includes forming a transfer foil that includes a porous silicon carbide layer. A composite substrate is formed that includes the transfer foil and a support substrate. The transfer foil and the support substrate are brought into contact with each other and connected to each other. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite to the support substrate. The composite substrate is divided into a device substrate and a reclaim substrate. The device substrate includes the epitaxial layer and the reclaim substrate includes the support substrate.

Process flow for a stacked power diode and design of the resulting diode is disclosed. Blanket epitaxy over heavy doped wafers is performed. By controlling dopant addition during epitaxy, desired n-type, diode base, and p-type doping profiles and thicknesses achieved. V-groove pattern if formed on wafers by depositing mask film, lithography and anisotropic etch. Islands surrounded by V-grooves define individual diodes. V-grooves serve as side insulation. Next, oxidation step passivates V-grooves. Further, the mask film is stripped to open diode contact areas on both sides of wafers. Next high melting point metal and low melting point metal films are selectively electroplated on all open silicon surfaces. Stacking is performed on wafer level by bonding of desired wafer count by solid-liquid interdiffusion process. Wafer stacks are sawed into individual stacked diode dies along outer slopes of V-grooves. Final stacked devices can be used as DSRDdrift step recovery diodes. Compared to DSRDs made by known methods, better fabrication yield and higher pulse power electrical performance is achieved.

Provided is a semiconductor device, wherein a straight line extending from an end portion E1 in the extending direction of a contact hole for electrically connecting an emitter electrode and a front surface of a semiconductor substrate toward a back surface of the semiconductor substrate is defined as a first perpendicular line, a straight line forming a predetermined angle 1 with respect to the first perpendicular line and passing through the end portion E1 in the extending direction of the contact hole is defined as a first straight line, a position where the first straight line intersects a back surface of the semiconductor substrate is defined as a position M1, and the position M1 is located on an outer side of a cathode region in the extending direction.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

A diode structure includes a substrate having a first conductivity type, a first well region having a second conductivity type opposite to the first conductivity type and disposed in the substrate, a first doped region having the first conductivity type and disposed in the first well region, a ring-shaped well region having the second conductivity type, disposed in the first well region and surrounding the first doped region, an anode disposed on the first doped region, a second well region having the second conductivity type, separated from the first well region and disposed in the substrate, a second doped region having the second conductivity type and disposed in the second well region, and a cathode disposed on the second doped region.

A diode structure includes a substrate having a first conductivity type, a first well region having a second conductivity type opposite to the first conductivity type and disposed in the substrate, a first doped region having the first conductivity type and disposed in the first well region, a ring-shaped well region having the second conductivity type, disposed in the first well region and surrounding the first doped region, an anode disposed on the first doped region, a second well region having the second conductivity type, separated from the first well region and disposed in the substrate, a second doped region having the second conductivity type and disposed in the second well region, and a cathode disposed on the second doped region.

A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.

A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.

The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.