A semiconductor device includes: opposed first and second metal plates; a plurality of semiconductor elements each interposed between the first metal plate and the second metal plate; a metal block interposed between the first metal plate and each of the semiconductor elements; a solder member interposed between the first metal plate and the metal block and connecting the first metal plate to the metal block; and a resin molding sealing the semiconductor elements and the metal block. A face of the first metal plate, which is on an opposite side of a face of the first metal plate to which the metal block is connected via the solder member, is exposed from the resin molding. The first metal plate has a groove formed along an outer periphery of a region in which the solder member is provided, the groove collectively surrounding the solder member.

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 110.sup.9 A/cm.sup.2 to 110.sup.4 A/cm.sup.2 in a rated voltage V.sub.R.

An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p.sup.+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p.sup.+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

A vertical gallium nitride (GaN) PN diode uses epitaxial growth of a thick drift region with a very low carrier concentration and a carefully designed multi-zone junction termination extension to achieve high voltage blocking and high-power efficiency. An exemplary large area (1 mm.sup.2) diode had a forward pulsed current of 3.5 A, an 8.3 m-cm.sup.2 specific on-resistance, and a 5.3 kV reverse breakdown. A smaller area diode (0.063 mm.sup.2) was capable of 6.4 kV breakdown with a specific on-resistance of 10.2 m-cm.sup.2, when accounting for current spreading through the drift region at a 45 angle.

A semiconductor diode, including: a first doped semiconductor region of a first conductivity type; a second doped semiconductor region of a second conductivity type opposite to the first conductivity type, arranged on top of and in contact with the upper surface of the first semiconductor region; a first conductive region arranged on top of and in contact with the upper surface of the second semiconductor region, the first conductive region comprising a through opening opposite a portion of the second semiconductor region; a second conductive region made of a material different from that of the first conductive region, coating the upper surface of the second semiconductor region opposite said opening; a cavity extending through the second conductive region and through the second semiconductor region opposite a portion of said opening; a dielectric region coating the lateral walls and the bottom of the cavity; a third conductive region coating the dielectric region on the lateral walls and at the bottom of the cavity, the third conductive region being further electrically in contact with the first and second conductive regions.

A semiconductor diode, including: a first doped semiconductor region of a first conductivity type; a second doped semiconductor region of a second conductivity type opposite to the first conductivity type, arranged on top of and in contact with the upper surface of the first semiconductor region; a first conductive region arranged on top of and in contact with the upper surface of the second semiconductor region, the first conductive region comprising a through opening opposite a portion of the second semiconductor region; a second conductive region made of a material different from that of the first conductive region, coating the upper surface of the second semiconductor region opposite said opening; a cavity extending through the second conductive region and through the second semiconductor region opposite a portion of said opening; a dielectric region coating the lateral walls and the bottom of the cavity; a third conductive region coating the dielectric region on the lateral walls and at the bottom of the cavity, the third conductive region being further electrically in contact with the first and second conductive regions.

A two-dimensional heterostructure is synthesized by producing a patterned first two-dimensional material on a growth substrate. The first two-dimensional material is patterned to define at least one void through which an exposed region of the growth substrate is exposed. Seed molecules are selectively deposited either on the exposed region of the growth substrate or on the patterned first two-dimensional material. A second two-dimensional material that is distinct from the first two-dimensional material is then grown from the deposited seed molecules.