Patent classifications
H01L39/00
Light-controlled superconductor
A light-controlled superconductor uses electrons as carriers, which includes a light source and a sealed tube, wherein the sealed tube is made of glass or plastic. The sealed tube is filled with electron gas, and the light source produces incident light, and under the irradiation of the incident light, electrons will be forced to vibrate and behave similarly to vibrating electric dipoles, and emit secondary electromagnetic waves, so that the average distance between the electrons in the sealed tube is much smaller than the wavelength of the incident light, causing the vibrating electrons to be in a near-field of each other. When the electric field intensity direction of the incident light and the electric moments of two vibrating electrons are in the same radial straight line and are in the same direction, there exists an attractive force among the vibrating electrons.
Superconducting resonator to limit vertical connections in planar quantum devices
A set of superconducting devices is interconnected in a lattice that is fabricated in a single two-dimensional plane of fabrication such that a superconducting connection can only reach a first superconducting device in the set while remaining in the plane by crossing a component of a second superconducting device that is also located in the plane. A superconducting coupling device having a span and a clearance height is formed in the superconducting connection of the first superconducting device. A section of the superconducting coupling device is separated from the component of the second superconducting device by the clearance in a parallel plane. A potential of a first ground plane on a first side of the component is equalized with a second ground plane on a second side of the component using the superconducting coupling device.
Buffer layer to prevent etching by photoresist developer
A method includes: providing a device having a first layer and a second layer in contact with a surface of the first layer, in which the second layer includes a first superconductor material; forming a buffer material on the second layer to form an etch buffer layer, in which an etch rate selectivity of the buffer material relative to the second layer upon exposure to a photoresist developer is such that the underlying second layer is not etched during exposure of the buffer layer to the photoresist developer; depositing and removing a selected portion of a resist layer to uncover a first portion of the etch buffer layer, wherein removing the selected portion of the resist layer comprises applying the photoresist developer to the selected portion of the resist layer.
Device for determining the parameters of strip-type superconductors
A device for determining the parameters of strip-type superconductors includes a generator, a generator frequency-setting element, an inductance coil connected to the generator, a receiver, a receiver frequency-setting element, and an inductance coil connected to the receiver. The generator and receiver frequency-setting elements are same type narrow-band elements. The pass bands of the generator and receiver frequency-setting elements coincide through at least half of the bandwidth of the frequency-setting element having a narrower band pass width. The generator and receiver inductance coils are arranged with a gap between the same, making it possible for a strip-type superconductor to be placed between the inductance coils. The device is provided with a temperature sensor comprising a thermistor in contact with the superconductor. The device enables highly accurate and reproducible measurement results.
SEMICONDUCTOR AND FERROMAGNETIC INSULATOR HETEROSTRUCTURE
A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.
Antenna-based quibit annealing method
Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.
Quantum device comprising FET transistors and qubits co-integrated on the same substrate
Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.
REDUCED THERMAL RESISTANCE ATTENUATOR ON HIGH-THERMAL CONDUCTIVITY SUBSTRATES FOR QUANTUM APPLICATIONS
Techniques for facilitating reduced thermal resistance attenuator on high-thermal conductivity substrates for quantum applications are provided. A device can comprise a substrate that provides a thermal conductivity level that is more than a defined thermal conductivity level. The device can also comprise one or more grooved transmission lines formed in the substrate. The one or more grooved transmission lines can comprise a powder substance. Further, the device can comprise one or more copper heat sinks formed in the substrate. The one or more copper heat sinks can provide a ground connection. Further, the one or more copper heat sinks can be formed adjacent to the one or more grooved transmission lines.
MICROWAVE COMBINER AND DISTRIBUTER FOR QUANTUM SIGNALS USING FREQUENCY-DIVISION MULTIPLEXING
A technique relates to a superconducting microwave combiner. A first filter through a last filter connects to a first input through a last input, respectively. The first filter through the last filter each has a first passband through a last passband, respectively, such that the first passband through the last passband are each different. A common output is connected to the first input through the last input via the first filter through the last filter.
Semiconductor fabrication
In-situ patterning of semiconductor structures is performed using one or more shadow walls in conjunction with an angled deposition beam. A shadow wall protrudes outwardly from the surface of a substrate to define an adjacent shadow region in which deposition is prevented due to the shadow wall inhibiting the passage of the angled deposition beam. Hence, deposition will not occur on a surface portion of a semiconductor structure within the shadow region. Shadow walls can thus be used to achieve selective patterning of semiconductor structures. The shadow walls themselves are formed of semiconductor. In one implementation, the semiconductor structure and the one or more shadow walls used to selectively pattern it may be formed using selective area growth (SAG).