A set of superconducting devices is interconnected in a lattice that is fabricated in a single two-dimensional plane of fabrication such that a superconducting connection can only reach a first superconducting device in the set while remaining in the plane by crossing a component of a second superconducting device that is also located in the plane. A superconducting coupling device having a span and a clearance height is formed in the superconducting connection of the first superconducting device. A section of the superconducting coupling device is separated from the component of the second superconducting device by the clearance in a parallel plane. A potential of a first ground plane on a first side of the component is equalized with a second ground plane on a second side of the component using the superconducting coupling device.

A cavity oscillator comprising: an amplifier operable to provide energy to a local oscillating signal; a superconducting resonant cavity arranged to receive the local oscillating signal and being operable to reflect a portion of the local oscillating signal for use in a feedback circuit, to support an electromagnetic wave related to the local oscillating signal in a desired TM mode, and to output a filtered signal of a desired frequency or frequencies based on the geometry of the cavity; a feedback circuit operable to generate an error signal based on the local oscillating signal and the reflected signal; and a phase shifter arranged operable to adjust the filtered signal based on the error signal to generate an adjusted filtered signal. The amplifier can amplify the adjusted filtered signal.

An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.

A method of fabricating an electrical contact junction that allows current to flow includes: providing a substrate including a first layer of superconductor material; removing a native oxide of the superconductor material of the first layer from a first region of the first layer; forming a capping layer in contact with the first region of the first layer, in which the capping layer prevents reformation of the native oxide of the superconductor material in the first region; forming, after forming the capping layer, a second layer of superconductor material that electrically connects to the first region of the first layer of superconductor material to provide the electrical contact junction that allows current to flow.

A set of superconducting devices is interconnected in a lattice that is fabricated in a single two-dimensional plane of fabrication such that a superconducting connection can only reach a first superconducting device in the set while remaining in the plane by crossing a component of a second superconducting device that is also located in the plane. A superconducting coupling device having a span and a clearance height is formed in the superconducting connection of the first superconducting device. A section of the superconducting coupling device is separated from the component of the second superconducting device by the clearance in a parallel plane. A potential of a first ground plane on a first side of the component is equalized with a second ground plane on a second side of the component using the superconducting coupling device.

A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.

A semiconductor structure and methods of forming the semiconductor structure include a solder bump self-aligned to a through-substrate-via, wherein the solder bump and the through-substrate-via are formed of a conductive metal material, and wherein the through-substrate-via is coupled to a buried metallization layer, which is formed of a different conductive metal material.

This disclosure relates to compounds of formula (I):

L.sub.nD.sub.m(B.sub.xB.sub.1-x).sub.r(Z.sub.tZ.sub.1-t).sub.qM.sub.pA.sub.y(I),

in which n, m, x, r, t, q, p, L, D, B, B, Z, Z, M, and A are defined in the specification. These compounds can exhibit superconductivity at a high temperature.

A device for determining the parameters of strip-type superconductors includes a generator, a generator frequency-setting element, an inductance coil connected to the generator, a receiver, a receiver frequency-setting element, and an inductance coil connected to the receiver. The generator and receiver frequency-setting elements are same type narrow-band elements. The pass bands of the generator and receiver frequency-setting elements coincide through at least half of the bandwidth of the frequency-setting element having a narrower band pass width. The generator and receiver inductance coils are arranged with a gap between the same, making it possible for a strip-type superconductor to be placed between the inductance coils. The device is provided with a temperature sensor comprising a thermistor in contact with the superconductor. The device enables highly accurate and reproducible measurement results.