Patent classifications
B24D18/00
Printing a chemical mechanical polishing pad
A method of fabricating a polishing layer of a polishing pad includes successively depositing a plurality of layers with a 3D printer, each layer of the plurality of polishing layers deposited by ejecting a pad material precursor from a nozzle and solidifying the pad material precursor to form a solidified pad material.
Printing a chemical mechanical polishing pad
A method of fabricating a polishing layer of a polishing pad includes successively depositing a plurality of layers with a 3D printer, each layer of the plurality of polishing layers deposited by ejecting a pad material precursor from a nozzle and solidifying the pad material precursor to form a solidified pad material.
COMMAND ADDRESS INPUT BUFFER BIAS CURRENT REDUCTION
A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.
POLISHING PAD, PREPARATION METHOD THEREOF AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE USING SAME
The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.
POLISHING PAD, PREPARATION METHOD THEREOF AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE USING SAME
The embodiments relate to a polishing pad for use in a chemical mechanical planarization (CMP) process of semiconductors, to a process for preparing the same, and to a process for preparing a semiconductor device using the same. The polishing pad according to the embodiment adjusts the surface roughness characteristics of the polishing pad after polishing, whereby the polishing rate can be enhanced, and the surface residues, surface scratches, and chatter marks of the wafer can be remarkably reduced.
Methods of processing a polycrystalline diamond element
In an embodiment, a protective leaching cup may include a base portion, at least one sidewall defining an opening general opposite the base portion, and a receiving space in communication with the opening and at least partially defined by the base portion and the sidewall. The receiving space is sized and configured to receive at least a portion of the superabrasive element. A seal contact portion is located on an inner surface of the sidewall. The seal contact portion is configured to form a seal against the superabrasive element that is at least partially impermeable to fluid(s). At least one of the seal contact portion or the sidewall includes material(s) exhibiting a flexural modulus greater than about 150,000 psi at room temperature.
Methods of processing a polycrystalline diamond element
In an embodiment, a protective leaching cup may include a base portion, at least one sidewall defining an opening general opposite the base portion, and a receiving space in communication with the opening and at least partially defined by the base portion and the sidewall. The receiving space is sized and configured to receive at least a portion of the superabrasive element. A seal contact portion is located on an inner surface of the sidewall. The seal contact portion is configured to form a seal against the superabrasive element that is at least partially impermeable to fluid(s). At least one of the seal contact portion or the sidewall includes material(s) exhibiting a flexural modulus greater than about 150,000 psi at room temperature.
Polishing pad with pad wear indicator
The invention provides a polishing pad suitable for polishing integrated circuit wafers. A polyurethane polishing layer has a top surface and at least one groove in the polyurethane polishing layer. At least one copolymer wear detector located within the polyurethane polishing layer detects wear of the polishing layer adjacent the at least one groove. The at least one wear detector includes two regions, a first region being a fluorescent acrylate/urethane copolymer linked with a UV curable linking group and a second non-fluorescent region, The wear detector allows detecting wear of the polishing layer.
Grinding Tool and Method for Producing a Grinding Tool
A grinding tool has a main body having at least one fiber ply embedded in a binder. An abrasive layer is arranged on the main body. The at least one fiber ply is arranged in the binder in a partially movable manner. As a result, a relative movement that ensures high vibration and noise damping is achieved within the main body and within the at least one fiber ply.
Elastic Self-lubricating Polishing Tool
An elastic self-lubricating polishing tool includes an elastic grinding layer including an abrasive member and an elastic base layer affixed to the abrasive member, an absorbing layer absorbing and sustainedly releasing liquid inside of the absorbing layer, and an adhesive layer overlappedly connected with the elastic base layer of the elastic grinding layer and the absorbing layer. The elastic self-lubricating polishing tool is elastic and self-lubricating to sand and polish a surface of a workpiece.