A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

A semiconductor device includes a stacked structure of cell structures, an electrode structure, and a heating electrode. Each cell structure includes a capping layer, a selection layer, a buffer layer, a variable resistance layer, and a upper electrode layer sequentially stacked. The electrode structure is in an opening passing through the stacked structure, is electrically isolated from the buffer layer, the variable resistance layer, and the upper electrode layer, and is electrically connected to the selection layer. The heating electrode is between the variable resistance layer and the upper electrode layer and operates to transfer heat to the variable resistance layer.

An apparatus for non-volatile memory, and more specifically a ReRAM device with a buried resistive memory cell. The memory cell includes a first contact disposed on a substrate, an active layer, a second contact, a first diffused zone disposed within the active layer, a second diffused zone disposed within the active layer, and an active switching zone disposed within the active layer in between the first diffused zone and the second diffused zone. In one embodiment, the active zone may be doped by diffusion or ion implantation and/or may be fabricated utilizing a self-aligned process. In another embodiment, the memory cell may combine a deep implant and shallow diffusion well to create the active zone. The vertically and laterally isolated buried resistive memory cell concentrates the electric field away from the edges of the device and eliminates the effects of interface impurities and contaminants.

A switch device according to an embodiment of the technology includes a first electrode, a second electrode that is disposed to face the first electrode, and a switch layer that is provided between the first electrode and the second electrode. The switch layer contains a chalcogen element. The switch layer includes a first region and a second region which have different composition ratios of one or more of chalcogen elements or different types of the one or more of chalcogen elements. The first region is provided close to the first electrode. The second region is provided closer to the second electrode than the first region.

A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.

Provided herein may be an electronic device including a semiconductor memory. The semiconductor memory may include: first column lines and sub-column lines extending in a first direction; first row lines extending in a second direction; first tiles including first memory cells connected between the first column lines and the first row lines; first contact plugs coupled to the sub-column lines and disposed between the first tiles in the first direction; second contact plugs coupled to the first row lines and disposed between the first tiles in the second direction; and a first connection structure partially coupling the first column lines to the sub-column lines such that the longer a current path on a first row line from a selected first memory cell to the corresponding second contact plug, the shorter a current path from the selected first memory cell to the corresponding first contact plug.

Present disclosure provides a phase change memory structure, including a transistor region, a phase change material over the transistor region, a heater over the transistor region and in contact with the phase change material, and a dielectric layer surrounding the heater and the phase change material. The heater includes a first material having a first thermal conductivity, the first material disposed at a periphery of the heater, and a second material having a second thermal conductivity greater than the first thermal conductivity, the second material disposed at a center of the heater. Present disclosure also provides a method for manufacturing the phase change memory structure described herein.

A memory device including a via opening through a dielectric layer and an inert electrode having a conformal thickness present on sidewalls but recessed from the top of the via and a base surface of the via opening through the dielectric layer. A metal oxide layer provides a filament forming layer for the memory device and is present in direct contact with the inert electrode. The metal oxide layer also has a conformal thickness and has vertically orientated portions on the portion of the inert electrode overlying the sidewalls of the via opening, and horizontally orientated portions on the portion of the inert electrode overlying the base of the via opening. A reactive electrode is in direct contact with the metal oxide layer. Switching of the memory device includes a laterally orientated direction across the vertically orientated portion of the metal oxide layer in regions not modified by patterning of the conformal metal-oxide layer.

This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.

A storage apparatus according to embodiments includes: a first interlayer insulating film extending in a first direction; a second interlayer insulating film extending in the first direction; a first conductive layer extending in the first direction and provided between the first interlayer insulating film and the second interlayer insulating film; a second conductive layer extending in a second direction intersecting the first direction; a resistance change layer including a first portion provided between the first interlayer insulating film and the second interlayer insulating film and including a second portion provided between the second conductive layer and the first interlayer insulating film, between the second conductive layer and the first conductive layer, and between the second conductive layer and the second interlayer insulating film; and a sidewall insulating film provided between the first portion and the first interlayer insulating film and between the first portion and the second interlayer insulating film.