A vanadium dioxide (VO.sub.2)-based threshold switch device exhibiting current-controlled negative differential resistance (S-type NDR), an electrical oscillator circuit based on the threshold switch device, a wafer including a plurality of said devices, and a method of manufacturing said device are provided. The VO.sub.2-based threshold switch device exhibits volatile resistance switching and current-controlled negative differential resistance from the first time a sweeping voltage or voltage pulse is applied across the device without being treated with an electroforming process. Furthermore, the device exhibits substantially identical switching characteristics over at least 10.sup.3 switching operations between a high resistance state (HRS) and a low resistance state (LRS), and a plurality of threshold switch devices exhibits a threshold voltage V.sub.T spreading of less than about 25%. The threshold switch device may be included in an oscillator circuit to produce an astable oscillator that may serve as a functional building block in spiking-neuron based neuromorphic computing.

A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring structure is formed overlying the first dielectric material. The method forms one or more first structure comprising a junction material overlying the first wiring structure. A second structure comprising a stack of material is formed overlying the first structure. The second structure includes a resistive switching material, an active conductive material overlying the resistive switching material, and a second wiring material overlying the active conductive material. The second structure is configured such that the resistive switching material is free from a coincident vertical sidewall region with the junction material.

A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.

Provided is a multi-negative differential resistance device. The multi-negative differential resistance device includes a first negative differential resistance device and a second negative differential resistance device connected in parallel with the first negative differential resistance device, and a peak and a valley of the first negative differential resistance device and a peak and a valley of the second negative differential resistance device are synthesized, and, thus, the multi-negative differential resistance device has two peaks and two valleys.

Disclosed are a semiconductor memory device and a method of manufacturing the same. A first conductive line extends in a first direction on a substrate and has a plurality of protrusions and recesses that are alternately formed thereon. A second conductive line is arranged over the first conductive line in a second direction such that the first and the second conductive lines cross at the protrusions. A plurality of memory cell structures is positioned on the protrusions of the first conductive line and is contact with the second conductive line. A thermal insulating plug is positioned on the recesses of the first conductive line and reduces heat transfer between a pair of the neighboring cell structures in the first direction. Accordingly, the heat cross talk is reduced between the neighboring cell structures along the conductive line.

Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.

Dielectric wall structures are formed through a stack of a doped semiconductor material layer, a planar insulating spacer layer, and a sacrificial matrix layer. Gate electrode rails are formed through the dielectric wall structures and the sacrificial matrix layer. A two-dimensional array of rectangular openings is formed by removing remaining portions of the sacrificial matrix layer. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of rectangular openings. Gate dielectrics are formed on sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surround gates is formed, which may be employed as access transistors of a three-dimensional memory device.

Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.

The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.