A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

A method for forming a resistive random access memory structure. The resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

A three-dimensional memory device includes a stacking structure, memory pillars, and conductive pillars. The stacking structure includes stacking layers stacked along a vertical direction, each stacking layer including a gate layer, a gate dielectric layer, and a channel layer. The gate layer, the gate dielectric layer, and the channel layer extend along a horizontal direction, and the gate dielectric layer is disposed between the gate layer and the channel layer. The memory pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. Each memory pillar comprises a first electrode, a second electrode, and a switching layer between the first and second electrodes. The conductive pillars extend along the vertical direction and are laterally separated and in contact with the channel layer of each stacking layer. The memory pillars and the conductive pillars are alternately arranged along the horizontal direction.

At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

Disclosed is a resistive switching element. The resistive switching element includes a first oxide layer and a second oxide layer stacked one on top of the other such that an interface is present therebetween, wherein the first oxide layer and the second oxide layer are made of different metal oxides; two-dimensional electron gas (2DEG) present in the interface between the first oxide layer and the second oxide layer and functioning as an inactive electrode; and an active electrode disposed on the second oxide layer, wherein when a positive bias is applied to the active electrode, an electric field is generated between the active electrode and the two-dimensional electron gas, such that the second oxide layer is subjected to the electric field, and active metal ions from the active electrode are injected into the second oxide layer. The resistive switching element realizes highly uniform resistive switching operation.

Various embodiments may provide an electronic synapse device. The electronic synapse device may include a body including a doped chalcogenide layer including a chalcogenide material and a dopant. The electronic synapse device may also include a drain electrode in contact with the body. The electronic synapse device may further include a source electrode in contact with the body. The electronic synapse device may additionally include a gate electrode including an electrode contact layer in contact with the doped chalcogenide layer. The electrode contact layer may be any one selected from a group consisting of an electrically conductive layer including an electrically conductive material and a dopant layer including the dopant.

An information processing device, including a resistive analog neuromorphic device element having a pair of electrodes and an oxide layer provided between the pair of electrodes, and a parallel circuit having a low resistance component and a capacitance component. The parallel circuit and the resistive analog neuromorphic device element are connected in series.

A method of forming a phase change switching device includes providing a substrate, forming first and second RF terminals on the substrate, forming a strip of phase change material on the substrate that is connected between the first and second RF terminals, forming a heating element adjacent to the strip of phase change material such that the heating element is configured to control a conductive state of the strip of phase change material. The first and second RF terminals and the heating element are formed by a lithography process that self-aligns the heating element with the first and second RF terminals