A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The semiconductor structure includes a dielectric layer and a transistor. The transistor is at least partially disposed in the dielectric layer. The transistor includes a gate electrode, a gate dielectric layer, a source electrode, a drain electrode and a semiconductor layer. The gate dielectric layer is disposed over the gate electrode. The source electrode and the drain electrode are disposed over the gate dielectric layer and contact the gate dielectric layer. The semiconductor layer is disposed over the gate dielectric layer.

Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers include a first layer stack of a first transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material. The stack of layers can include a second layer stack of a second transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material, the second layer stack associated with a second transistor structure. The first and second transistor structures are separated by one or more dielectric materials. The method can include forming a channel opening in the stack. The method includes selectively forming a first channel structure within the channel opening and selectively forming a second channel structure within the channel opening.

Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers include a first layer stack of a first transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material. The stack of layers can include a second layer stack of a second transistor structure including at least three layers of a conductive material separated by one or more layers of at least one dielectric material, the second layer stack associated with a second transistor structure. The first and second transistor structures are separated by one or more dielectric materials. The method can include forming a channel opening in the stack. The method includes selectively forming a first channel structure within the channel opening and selectively forming a second channel structure within the channel opening.

The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.

A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.

A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.