A structure includes an off-axis Si substrate with an overlying s-Si.sub.1-xGe.sub.x layer and a BOX between the off-axis Si substrate and the s-Si.sub.1-xGe.sub.x layer. The structure further includes pFET fins formed in the s-Si.sub.1-xGe.sub.x layer and a trench formed through the s-Si.sub.1-xGe.sub.x layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si.sub.1-xGe.sub.x layer has a value of x that results from a condensation process that merges an initial s-Si.sub.1-xGe.sub.x layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.

A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.

Provided is a transistor containing a semiconductor with low density of defect states, a transistor having a small subthreshold swing value, a transistor having a small short-channel effect, a transistor having normally-off electrical characteristics, a transistor having a low leakage current in an off state, a transistor having excellent electrical characteristics, a transistor having high reliability, or a transistor having excellent frequency characteristics. An insulator is formed, a layer is formed over the insulator, oxygen is added to the insulator through the layer, the layer is removed, an oxide semiconductor is formed over the insulator to which the oxygen is added, and a semiconductor element is formed using the oxide semiconductor.

Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

A semiconductor device that can extend the range of adaptable sampling rate when performing analog/digital conversion is provided. The semiconductor device includes a plurality of sample-and-hold circuits storing an analog signal and a plurality of converter circuits having a function of converting the analog signal stored in the sample-and-hold circuit into a digital signal. The sample-and-hold circuit includes a switch and a capacitor that is supplied with an analog signal through the switch. The switch includes an oxide semiconductor in a channel formation region.

A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.

A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first transistor, a first insulator over the first transistor, a second transistor over the first insulator, a second insulator over the second transistor, and a capacitor over the second insulator. The first insulator has a barrier property against oxygen and hydrogen. The second transistor includes an oxide semiconductor. The second insulator includes an oxygen-excess region. The capacitor includes a first electrode, a second electrode, and a dielectric between the first electrode and the second electrode. The dielectric includes a third insulator having a barrier property against oxygen and hydrogen. The first insulator and the third insulator are in contact with each other on an outer edge of a region where the second transistor is located so that the second transistor and the second insulator are enclosed by the first insulator and the third insulator.