A method of manufacturing a semiconductor package may include: preparing a semiconductor wafer including rear pads and a rear insulating layer surrounding the rear pads, the rear insulating layer including first recesses spaced apart from the rear pads in a first lateral direction; preparing second semiconductor chips including front pads and a front insulating layer surrounding the front pads, the front insulating layer including second recesses spaced apart from the front pads in the first lateral direction; forming an air gap between the first recesses and the second recesses in a vertical direction by disposing the second semiconductor chips on the semiconductor wafer, the rear pads contacting the front pads; and bonding the rear insulating layer and the front insulating layer to each other and bonding the rear pads and the front pads to each other by performing a thermal compression process.

A semiconductor device includes: a substrate with a cell region and a chip guard region, the chip guard region surrounding the cell region; a first chip guard extending over the chip guard region in a first direction; a second chip guard extending over the chip guard region in the first direction, the second chip guard being spaced apart from the first chip guard; and a third chip guard extending over the chip guard region in a second direction, the second direction intersecting the first direction. The first chip guard includes a first end portion, the second chip guard includes a second end portion, and the third chip guard includes a third end portion that is disposed between the first end portion and the second end portion.

A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.

A light emitting device may include: a substrate including a plurality of unit light emitting regions; and first to fourth insulating layers sequentially on the substrate. Each of the unit light emitting regions may include: at least one light emitting element on the first insulating layer, the at least one light emitting element having a first end portion and a second end portion in a length direction thereof; first and second partition walls on the substrate, and the first and second partition walls being spaced apart from each other; a first reflective electrode on the first partition wall and a second reflective electrode on the second partition wall; a first contact electrode on the first reflective electrode, the first contact electrode connecting the first reflective electrode and the first end portion of the light emitting element; a second contact electrode on the second reflective electrode, the second contact electrode connecting the second reflective electrode and the second end portion of the light emitting element; and a conductive pattern provided between the first insulating layer and the first contact electrode, the conductive pattern surrounding the first and second reflective electrodes when viewed on a plane.

A semiconductor package includes a package substrate including a base substrate including a redistribution layer, pads disposed on first and second surfaces of the base substrate and connected to the redistribution layer, and a protective layer having a mounting region in which first openings respectively exposing first pads among the pads and a second opening exposing second pads among the pads and a portion of the second surface are disposed on the second surface; a semiconductor chip disposed on the mounting region and connected to the pads through the first openings and the second opening; and a sealing material covering a portion of the semiconductor chip and extending into the second opening. Four first openings among the first openings are respectively disposed adjacent to respective corners of the mounting region. The second opening is disposed to divide the four first openings into at least two groups.

This insulating chip comprises: an insulating layer; a first coil and a second coil disposed in the insulating layer; and a second electrode electrically connected to the second coil. The second coil has an annular shape in a plan view as seen from the Z direction. The second electrode includes a second inner electrode that is disposed, when viewed in the plan view, over both an inner region surrounded by the second coil and a region overlapping the second coil. A passivation film formed on the upper surface of the insulating layer includes a second inner opening that exposes at least a portion of the second inner electrode. The second inner opening is formed at a position that is over the second inner electrode, and is over both the inner region and the region overlapping the second coil.

A composite component containing one or more electronic components. The composite component includes a Si base layer having a first main surface, and a second main surface facing the first main surface, a redistribution layer disposed on the first main surface, a through-Si via extending through the Si base layer and the adhesive layer to electrically connect the redistribution layer and the electronic component, and extending through the Si base layer, an electronic component electrically connected to the through-Si via, and disposed on the second main surface, sidewall portions surrounding the electronic component, and disposed to form a recessed portion together with the Si base layer, and a resin sealing portion sealing the electronic component.

Embodiments disclosed herein include optical communication modules and optoelectronic packages. In an embodiment, an optical communication module comprises a substrate, a transistor over the substrate, an array of micro light emitting diodes (LEDs) over the transistor, and a connector over the array of micro LEDs.

A semiconductor device includes a plurality of semiconductor modules. Each of the plurality of semiconductor modules includes: a base plate having a first surface and a second surface, the first surface being exposed to the outside of the semiconductor module, the second surface being on a side opposite to the first surface; an insulated substrate with a circuit pattern provided thereon; a semiconductor chip bonded to the circuit pattern; a sealer that seals the insulated substrate and the semiconductor chip; and a first main electrode and a second main electrode drawn out of the sealer in a direction opposite to a direction from the sealer toward the base plate. The semiconductor module has a planar shape with four corners, and has a rotationally symmetric shape.

A semiconductor device assembly can include a first semiconductor device comprising CMOS circuitry at a first active surface and a second semiconductor device having a footprint smaller than that of the first semiconductor device and including memory array circuitry at a second active surface hybrid-bonded to the first active surface. The assembly can further include a gapfill material directly contacting the first active surface of the first semiconductor device and having an upper surface coplanar with a back surface of the second semiconductor device, and a metallization layer disposed over the second semiconductor device and the gapfill material. The metallization layer can include conductive structures operably coupled to the second semiconductor device through back-side contacts of the second semiconductor device. The assembly can further include a plurality of bond pads disposed at an upper surface of the metallization layer and coupled to the conductive structures of the metallization layer.