A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.

A method for manufacturing a semiconductor package includes: providing a leadframe having component positions each of which includes a die pad; providing semiconductor dies each having a first power electrode on a first main surface and a second power electrode on a second main surface; mounting a respective semiconductor die onto the die pad of a respective component position of the leadframe such that the first power electrode is attached to the die pad; mounting a clip onto the dies such that the clip is attached to a respective second power electrode; embedding at least the side faces of the dies and inner surfaces of the leadframe and clip in a mold compound to form a subassembly; and cutting through the clip and leadframe at positions between neighbouring component positions.

Disclosed is a semiconductor package device comprising a lower redistribution substrate, a first semiconductor chip on the lower redistribution substrate, vertical structures on the lower redistribution substrate, and a first molding member on the lower redistribution substrate and on the first semiconductor chip and the vertical structures. The vertical structure includes a first post having a first diameter, a second post on the first post and having a second diameter, and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters are different from each other. The third diameter is greater than the second diameter.

A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.

A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.