A semiconductor package has a first semiconductor package which includes a first redistribution structure, a first semiconductor chip on a lower surface of the first redistribution structure, a first encapsulant on at least a portion of the first semiconductor chip, a second redistribution structure on the first encapsulant, and a conductive post electrically connecting the first redistribution structure and the second redistribution structure through the first encapsulant; and a second semiconductor package which is on an upper surface of the first redistribution structure and comprises a third redistribution structure, a second semiconductor chip on the third redistribution structure, and a second encapsulant on at least a portion of the second semiconductor chip, wherein the first encapsulant integrally covers each of a lower surface and a side surface of the first semiconductor chip.

A semiconductor package structure includes a redistribution structure layer, at least one chip, an encapsulant, and multiple solder balls. The redistribution structure layer includes multiple first connectors located on a first side. Each first connector includes a connecting pad, a soldering pad, and multiple conductive blind holes located between the connecting pad and the soldering pad. The conductive blind holes are disposed separately from each other and connect the connecting pad and the soldering pad. The chip is disposed on a second side of the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the second side and at least covers the chip and the second side. The solder balls are disposed on the first side of the redistribution structure layer and electrically connected to the redistribution structure layer. The solder balls are respectively connected to the connecting pad of each first connector.

A semiconductor package includes: a lower redistribution structure including a lower redistribution layer; external connection bumps below the lower redistribution structure; a lower chip structure on the lower redistribution structure; an encapsulant at least partially encapsulating the lower chip structure; an upper encapsulating layer on the encapsulant; an adhesive layer on an upper surface of the lower chip structure; a plurality of posts extending through the encapsulant and electrically connected to the lower redistribution layer; an upper chip structure on the upper encapsulating layer and electrically connected to the plurality of posts; a heat dissipation member on one side of the upper chip structure and overlapping the lower chip structure in a vertical direction; and a heat transfer material layer extending through the upper encapsulating layer and the adhesive layer and disposed between the heat dissipation member and the lower chip structure.

A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

There is provided a memory device including a first chip including a first normal region, the first region including a plurality of first normal connectors on a first surface and configured to be provided with signals used during an operation of memory cells, and a first test region including a plurality of first connectors on the first surface and electrically connected to each other, and a second chip. The second chip includes a second normal region including a plurality of second normal connectors, and configured to provide signals used during the operation of the memory cells to the first normal connectors, and a second test region including a plurality of first and second test connectors on the second surface so as not to overlap the plurality of first connectors in the first direction, and configured to not be provided with signals used during the operation of the memory cells.

A semiconductor package includes a first chip structure on a first substrate and a first molding layer surrounding the first chip structure on the first substrate, wherein the first chip structure includes a first chip including a PIC on the first substrate, a second chip including an EIC on the first chip, a transparent layer horizontally spaced from the second chip on the first chip, a microlens layer on the transparent layer; and a second molding layer surrounding the second chip, the transparent layer, and the microlens layer on the first chip, the semiconductor package further includes a first insulating layer on an upper surface of the first chip and a second insulating layer on a lower surface of the transparent layer, and the first and second 10 insulating layers are in contact with each other, and the first and second insulating layers are integrally formed of the same material.

According to an aspect of the present disclosure, a semiconductor device includes a cell structure including a gate stacking structure in a first region and an insulation structure in a second region, a first wiring portion disposed on a first surface of the cell structure, a second wiring portion disposed on a second surface of the cell structure opposite to the first surface, a channel structure at least partially penetrating the gate stacking structure and being electrically coupled with the first wiring portion and the second wiring portion, and a capacitor structure including a plurality of penetration structures. The gate stacking structure includes a plurality of gate electrodes while interposing an interlayer insulation layer therebetween. Each of the plurality of penetration structures at least partially penetrates at least a portion of the insulation structure.

An electronic package and a manufacturing method thereof are provided. The electronic package includes an electronic component and a shielding layer. The electronic component has an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface and the active surface. The shielding layer is disposed on the electronic component and directly contacts and completely covers the inactive surface and the side surface. The shielding layer is formed directly on the surface of the electronic component, thereby shielding electromagnetic interference, reducing the size of the electronic package, and lowering production costs.

A device structure includes at least one alternating stack of respective layers and electrically conductive layers, a memory opening vertically extending through each layer within the at least one alternating stack, a memory opening fill structure located in the memory opening, and a contact via structure in contact with a first electrically conductive layer of the electrically conductive layers. An outer blocking dielectric layer contacts the first electrically conductive layer, laterally surrounds the contact via structure, and vertically extends continuously through the alternating stack and the at least one retro-stepped dielectric material portion.

A package structure and a formation method are provided. The method includes forming multiple patterned material elements over a carrier substrate, and the patterned material elements are more thermal conductive than copper. The method also includes forming a protective layer laterally surrounding each of the patterned material elements. The method further includes bonding a chip-containing structure to a first patterned material element of the patterned material elements through dielectric-to-dielectric bonding and metal-to-metal bonding.