A method for making semiconductor package, wherein the method comprises: providing a substrate and a plurality of semiconductor dice; forming an integrated interposer block comprising a first interposer layer, a second interposer layer and a dummy portion, wherein the integrated interposer block defines a central axis, wherein the first interposer layer and the second interposer layer are symmetric with respect to the central axis to form an interposer pyramid; removing the dummy portion from the integrated interposer block to form a pair of step structures, wherein each step structure comprises two step surfaces; attaching the interposer pyramid on the substrate; attaching a first pair of semiconductor dice on the substrate; attaching a second pair of semiconductor dice on the first interposer layer and the first pair of semiconductor dice; and forming an encapsulant layer on the substrate to encapsulate the interposer pyramid and the semiconductor dice.

A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.

Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.

A dual sided molded package has a substrate with pads of varying size configured to receive electrically conductive interconnect members thereon. The pads include first pads that have a larger surface area than a surface area of second pads. In one implementation, one or more first pads are proximate the corners of the substrate. First interconnect members are attached to the first pads and second interconnect members are attached to the second pads. The first interconnect members have an exposed solderable area that is substantially equal to the surface area of the first pads, and the second interconnect members have an exposed solderable area that is substantially equal to the surface area of the second pads. The first exposed solderable area is larger than the second exposed solderable area.

Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.

The present disclosure provides an electronic device including a first electronic unit, a second electronic unit, a circuit layer, a protection layer, and a flexible member. The first electronic unit is electrically connected to the second electronic unit through the circuit layer. The protection layer is disposed corresponding to the first electronic unit and the second electronic unit, and the protection layer has an opening. At least a portion of the flexible member is disposed in the opening. The protection layer has a first Young's modulus, the flexible member has a second Young's modulus, and the first Young's modulus is greater than the second Young's modulus.

An antenna module is described. The antenna module include a ground plane in a multilayer substrate. The antenna module also includes a mold on the multilayer substrate. The antenna module further includes a conductive wall separating a first portion of the mold from a second portion of the mold. The conductive wall is electrically coupled to the ground plane. A conformal shield may be placed on a surface of the second portion of the mold. The conformal shield is electrically coupled to the ground plane.

In one example, an electronic device includes a first substrate and a second substrate. The first substrate includes a substrate first side, a substrate second side, and a first conductive structure. An inner electronic component is coupled to the first conductive structure proximate to the substrate second side. An outer electronic component is coupled to the first conductive structure proximate to the substrate first side. The outer electronic component includes a body and a groove in the body configured to couple with an external interconnect. Inner interconnects couple the first substrate to the second substrate. The first substrate, the second substrate, the inner electronic component, and the outer electronic component are in a stacked configuration. The inner electronic component is interposed between the first substrate and the second substrate. Other examples and related methods are also disclosed herein.