Exemplary embodiments provide systems and methods for portable medical ultrasound imaging. Preferred embodiments utilize a tablet touchscreen display operative to control imaging and display operations without the need for using traditional keyboards or controls. Certain embodiments provide ultrasound imaging system in which the scan head includes a beamformer circuit that performs far field sub array beamforming or includes a sparse array selecting circuit that actuates selected elements. Exemplary embodiments also provide an ultrasound engine circuit board including one or more multi-chip modules, and a portable medical ultrasound imaging system including an ultrasound engine circuit board with one or more multi-chip modules. Exemplary embodiments also provide methods for using a hierarchical two-stage or three-stage beamforming system, three dimensional ultrasound images which can be generated in real-time.

A structure including a redistribution structure comprising dielectric layers and conductive layers alternately stacked is provided, wherein a dielectric layer among the dielectric layers of the redistribution structure comprises a first surface, a conductive layer among the conductive layers of the redistribution structure comprising a second surface, and the conductive layer comprises a wiring layer and a seed layer; and an under-bump metallization (UBM) layer comprises a third surface, a fourth surface opposite to the third surface, and a sidewall surface extending from the third surface to the fourth surface, wherein a portion of the seed layer is between the wiring layer and the UBM layer, and the UBM is in contact with the dielectric layer.

Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.

A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

The present invention relates to the field of photonic integrated circuits and provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes an EIC chip and a PIC chip arranged on a substrate, the EIC chip is located between the PIC chip and the substrate. In embodiments, at least one EIC chip is disposed on a surface of a single PIC chip facing the substrate, and the EIC chip is mounted on the substrate through a connection structure. Therefore, the wiring of the PIC chip in the semiconductor device of the present invention is optimized such that the voltage drop due to long wiring distance can be suppressed, and the package structure of the semiconductor device is also optimized.

A semiconductor package includes a substrate, a logic die on the substrate, a base insulating layer on side surfaces and an upper surface of the logic die, an insulating layer through via extending through the base insulating layer at a side of the logic die, a high bandwidth memory on an upper surface of the base insulating layer, at least one optical structure on the upper surface of the base insulating layer, and at least one optical connector including an optical fiber configured to transmit an optical signal between the at least one optical structure and an external device, where the high bandwidth memory includes a plurality of memory dies stacked in a first direction that perpendicular to the upper surface of the base insulating layer and the at least one optical structure is connected to the logic die in the first direction.

A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.

A semiconductor package according to an embodiments includes a bridge chip including a connection pad; a redistribution structure disposed on the bridge chip and including a redistribution line connected to the connection pad of the bridge chip; and a first semiconductor chip and a second semiconductor chip disposed on the redistribution structure and spaced apart from each other along a horizontal direction and including a terminal pad connected to the redistribution line, wherein one of the connection pad and the terminal pad is positioned on a same plane as the redistribution structure, other pad of the connection pad and the terminal pad is positioned on a different plane from the redistribution structure, and a first conductive bump is disposed between the other pad and the redistribution structure.

A integrated light-emitting device includes: a base including a conductive wiring; a plurality of light-emitting devices mounted on the base and configured to emit a first light, each of the light-emitting devices comprising a light-emitting element and a encapsulant covering the light-emitting element; a light reflective film provided on an upper surface of the light-emitting element; and a plurality of light reflective members disposed between adjacent ones of the light-emitting devices. A ratio (H/W) of a height (H) of the encapsulant to a width (W) of a bottom surface of the encapsulant is less than 0.5. Each of the light-emitting devices has a batwing light distribution characteristics.

A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.