A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

A film package includes a base film including peripheral regions on opposite ends of the base film in a width direction and extending in a lengthwise direction, an inner region between the peripheral regions and extending in the lengthwise direction, and sprocket holes provided on the peripheral regions at a regular interval in the lengthwise direction, and a unit film package provided on the base film and defined by a cut line, the unit film package including a mount region on the inner region and a connection region provided in the lengthwise direction from the mount region, the connection region extending from the inner region toward a location between the sprocket holes in the lengthwise direction.

A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer and having an upper surface coplanar with an upper surface of the first semiconductor chip, a metal layer on the first semiconductor chip and the mold layer to be in contact with upper surfaces of the mold layer and the first semiconductor chip, and a second redistribution layer on the metal layer.

A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer and having an upper surface coplanar with an upper surface of the first semiconductor chip, a metal layer on the first semiconductor chip and the mold layer to be in contact with upper surfaces of the mold layer and the first semiconductor chip, and a second redistribution layer on the metal layer.

A semiconductor package includes a base chip including a base substrate and upper connection terminals disposed in an upper portion of the base substrate; a semiconductor chip stack including a plurality of semiconductor chips including lower pads and upper pads stacked in order on the base chip in a first direction and opposite to each other, and having through-vias electrically connecting the lower pads to the upper pads, and the plurality of semiconductor chips include a lowermost semiconductor chip and an uppermost semiconductor chip, and the lower pads of the lowermost semiconductor chip are in contact with the upper connection terminals; a dummy chip on the semiconductor chip stack; and a plurality of adhesive layers including a first adhesive layer on the uppermost semiconductor chip and a second adhesive layer on the first adhesive layer.

A semiconductor device includes a semiconductor substrate, a plurality of semiconductor dies, a dielectric layer, a connector, and a passivation layer. The plurality of semiconductor dies are stacked on one another and disposed over the semiconductor substrate. The dielectric layer cover a top surface and a side surface of the each of the plurality of semiconductor dies. The connector is disposed over a topmost one of the plurality of semiconductor dies. The passivation layer is disposed over the dielectric layer and laterally surrounds the connector, wherein, from a cross sectional view, an acute angle is included between an outermost side surface of the passivation layer and a bottom surface of the passivation layer.

A packaged electronic device comprises a power semiconductor die that includes a first terminal and a second terminal, a power substrate comprising a dielectric substrate having a first metal cladding layer on an upper surface thereof, an encapsulation covering the power semiconductor die and at least a portion of the power substrate, a first lead extending through the encapsulation that is electrically connected to the first terminal, and a second lead extending through the encapsulation that is electrically connected to the second terminal. The first terminal is bonded to the first lead via a first transient liquid phase solder joint.

A method includes bonding a first semiconductor die and a second semiconductor die to a substrate, where a gap is disposed between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, performing a plasma treatment to dope top surfaces and sidewalls of each of the first semiconductor die and the second semiconductor die with a first dopant, where a concentration of the first dopant in the first sidewall decreases in a vertical direction from a top surface of the first semiconductor die towards a bottom surface of the first semiconductor die, and a concentration of the first dopant in the second sidewall decreases in a vertical direction from a top surface of the second semiconductor die towards a bottom surface of the second semiconductor die, and filling the gap with a spin-on dielectric material.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.