A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

A semiconductor device comprises a III-N device including an insulating substrate. The insulating substrate includes a first side and a second side. The device further includes a III-N material structure on a first side of the insulating substrate, and a gate electrode, a source electrode, and a drain electrode on a side of the III-N material structure opposite the substrate. A backmetal layer on the second side of the insulating substrate, and a via hole is formed through the III-N material structure and the insulating substrate. A metal formed in the via-hole is electrically connected to the drain electrode on the first side of the substrate and electrically connected to the backmetal layer on the second side of the substrate.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

A method of manufacturing a semiconductor memory device of one embodiment includes a first resist forming process, a first step forming process, a second resist forming process, and a second step forming process. In the first resist forming process, a first resist layer is formed on the upper surface of the stacked body. In the first step forming process, a lower region of a first stepped portion and an upper region of a second stepped portion are simultaneously formed by etching processing performed via the first opening pattern. In the second resist forming process, a second resist layer having a second opening pattern is formed on the upper surface of the stacked body. In the second step forming process, the upper region of the first stepped portion and the lower region of the second stepped portion are simultaneously formed by etching processing performed via the second opening pattern.

A method of processing a substrate that includes: selectively depositing a self-assembled monolayer (SAM) on a metal line of the substrate, the SAM being in contact with the metal line, a surface of the substrate further including a first dielectric material that surrounds the metal line; selectively depositing a second dielectric material over the first dielectric material; forming a dielectric layer by depositing a third dielectric material over the second dielectric material and the SAM; and patterning the dielectric layer.

An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

Embodiments described herein may be related to apparatuses, processes, and techniques related to patterning and metallization to produce metal features on a substrate that have pitches less than 26 nm. Other embodiments may be described and/or claimed.

Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.

Embodiments of the present disclosure provide methods of forming a RDL structure with a flat passivation surface. Some embodiments provide a stop layer for chemical mechanical polishing disposed under a passivation layer. Some embodiments provide an extra thickness of passivation deposition and a sacrificial passivation layer for passivation polishing. Some embodiments provide a modified RDL pattern by inserting dummy pattern objects to adjust pattern density.