A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

A method includes forming a seed layer on a substrate. The seed layer includes a first metal. The method also includes forming a first metal layer over the seed layer. The first metal layer includes a second metal. The method further includes forming a second metal layer over the first metal layer. The second metal layer includes the first metal. The method includes converting at least a portion of the first metal layer into an alloy of the first metal and the second metal. The seed layer is then etched.

A semiconductor package structure includes a first package component, a second package component disposed over the first package component, a plurality of connectors between the first package component and the second package component, an underfill between the first package component and the second package component and surrounding the plurality of connectors, and a plurality of heat sink fibers in the underfill. A thermal conductivity of the plurality of heat sink fibers is greater than a thermal conductivity of the underfill.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

A power electronics converter may include: a converter commutation cell having a power circuit and a gate driver circuit, the power circuit including at least one power semiconductor switching element and at least one capacitor, wherein each power semiconductor switching element is embedded in a solid insulating material, wherein each power semiconductor switching element has at least three terminals including a gate terminal, wherein the gate driver circuit is electrically connected to and configured to provide switching signals to the gate terminal of each power semiconductor switching element, wherein a peak rated power output of the power electronics converter is greater than 25 KW, and wherein a total rated capacitance of the power circuit of the converter commutation cell divided by the peak rated power output of the power electronics converter is less than or equal to 5 nF/W.

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

A semiconductor structure and a memory are provided The semiconductor structure includes: a first active area pattern; a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern which are arranged at intervals in a first direction; a first connection pattern, arranged to connect the second gate pattern and the third gate pattern in parallel; a second connection pattern, arranged to connect the first gate pattern and the fourth gate pattern in parallel; at least two first contact hole patterns arranged in parallel; and at least two second contact hole patterns and at least two third contact hole patterns arranged in parallel.

The present disclosure provides a package structure. The package structure includes: a first die having a front surface and a back surface opposite to the front surface; and a first thermal management structure over the back surface. The first thermal management structure includes: a first copper-phosphorous alloy layer thermally coupled to and covering an entirety of the back surface of the first die.

The present disclosure provides a package structure and a method of manufacturing a package. The package structure includes a semiconductor die laterally encapsulated by an encapsulant, a redistribution structure and bumps. The redistribution structure is disposed on the semiconductor die and the encapsulant, and is electrically connected with the at least one semiconductor die. The bumps are disposed on the redistribution structure. The redistribution structure includes dielectric layers and metallic pattern layers sandwiched between the dielectric layers. The redistribution structure includes metallic pads on an outermost dielectric layer of the dielectric layers, and the outmost dielectric layer has undercut cavities beside the metallic pads.

A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.