A semiconductor unit includes: a semiconductor module including a semiconductor device and a horizontal terminal; a base plate including an upper surface to which the semiconductor module is bonded and a plurality of screw holes passing through the base plate from the upper surface to a lower surface; a cooler attached to the lower surface of the base plate and cooling the semiconductor module; and a plurality of screws screwed to the plurality of screw holes of the base plate, respectively, so that the cooler is attached to the lower surface of the base plate. A spot facing part having a depth smaller than a thickness of the base plate is provided to a part of at least one of the plurality of screw holes on a side of the upper surface of the base plate.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

An interconnect structure includes a plurality of first pads, a plurality of second pads, and a plurality of conductive lines. The first pads are arranged to form a first column-and-row array, and the second pads are arranged to form a second column-and-row array. The first column-and-row array, the second column-and-row array and the conductive lines are disposed in a same layer. The first pads in adjacent rows in the first column-and-row array are separated from each other by a first vertical distance from a plan view, the second pads in adjacent rows in the second column-and-row array are separated from each other by a second vertical distance from the plan view. A sum of widths of the conductive lines electrically connecting the first pads and the second pads in the same row is less than the first vertical distance and the second vertical distance from the plan view.

An electronics assembly includes a plurality of planar conductive metal sheets including a first conductive metal sheet, a second conductive metal sheet attached and electrically coupled to the first metal sheet, and a third conductive metal sheet attached and electrically coupled to the second metal sheet. The second metal sheet is located between the first and third conductive metal sheets. Air gaps are defined in the plurality of planar conductive metal sheets to form metal traces that define electrically isolated conductive paths from an outer surface of the first conductive metal sheet to an outer surface of the third conductive metal sheet in a multilevel conductive wiring network. The multilevel conductive wiring network can be attached and electrically coupled to a microchip and to one or more capacitors to form a power converter.

One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

A semiconductor device includes: a substrate including a component area and an edge area at least partially surrounding an outer perimeter of the component area; an upper insulating layer disposed on a first surface of the substrate; a recess formed in the upper insulating layer and extends downward along an outermost perimeter of the substrate in the edge area; and a trench formed in the upper insulating layer between the component area and the recess, and recessed downward beyond the recess, in the edge area.

Metallization structure for an integrated circuit. In one embodiment, an integrated circuit includes a metal-to-diffusion (MD) layer disposed over an active region of a cell, gates disposed over the active region of the cell, and a first metallization layer including M0 tracks disposed over the MD layer and the gates. The integrated circuit further includes a second metallization layer including M1 tracks disposed over the first metallization layer. The M1 tracks include first M1 tracks each having a first predetermined distance from an edge of the cell and second M1 tracks each having a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks.

A method of determining a height value of a wire loop on a wire bonding machine is provided. The method includes the steps of: (a) imaging at least a portion of a wire loop using an imaging system on a wire bonding machine to detect a path of the portion of the wire loop; (b) moving a wire bonding tool towards a first contact portion of the wire loop in the path; (c) detecting when a portion of a conductive wire engaged with the wire bonding tool contacts the first contact portion of the wire loop; and (d) determining a height value of the wire loop at the first contact portion based on a position of the wire bonding tool when the portion of the conductive wire contacts the first contact portion of the wire loop.