A power module comprises: an upper arm structure that includes a first semiconductor switch, a second semiconductor switch and a first diode; a lower arm structure that includes a third semiconductor switch, a fourth semiconductor switch and a second diode; a first gate driving board, attached with the upper arm, wherein the first gate driving board includes a first gate driver connected to a first gate of the first semiconductor switch and a second gate driver connected to a second gate of the second semiconductor switch; a second gate driving board, attached with the lower arm, wherein the second gate driving board includes a third gate driver connected to a third gate of the third semiconductor switch and a fourth gate driver connected to a fourth gate of the fourth semiconductor switch; etc.

A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

A method for making an electronic package is provided. The method includes providing a substrate strip comprising substrate assemblies, each substrate assembly comprises a first substrate and a second substrate connected to the first substrate via a flexible link, the first substrate comprises a first mounting surface, the second substrate comprises a second mounting surface that is not at a same side of the substrate assembly as the first mounting surface; disposing the substrate strip on a first carrier; attaching a first electronic component onto the first mounting surface; disposing the substrate strip on a second carrier with a plurality of cavities, the first electronic component is received within one of the plurality of cavities; attaching a second electronic component onto the second mounting surface; singulating the substrate assemblies from each other; and bending the flexible link to form an angle between the first substrate and the second substrate.

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Aspects of the present disclosure include systems, structures, circuits, and methods providing integrated circuit (IC) packages or modules having diagonalized leads. First and second semiconductor dies are disposed on a substrate. First and second coils are configured on the substrate for a transformer. The transformer may include a core. The leads or pins may be aligned along a diagonal of the package body, providing increased creepage. The IC packages and modules may include various types of circuits; in some examples, IC packages or modules may include a galvanically isolated gate driver or other high voltage circuit.

A semiconductor device includes: a supporting member having a wiring including a die-pad; a semiconductor element bonded to the die-pad; a wire bonded to the wiring and the semiconductor element; and a bonding layer that has a conductivity and bonds the die-pad and the semiconductor element. When viewed in a thickness direction of the semiconductor element, the die-pad includes a first region included inside a peripheral edge of the semiconductor element and a second region that is connected to the first region and extends farther then the peripheral edge of the semiconductor element. When viewed in the thickness direction, the wire is separated from the second region.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

An electronic module is provided that suppresses mispositioning of an internal connection terminal and a chip spacer, suppresses rotation of the chip spacer when solder is melted, and improves desired self-alignment effects. The electronic module includes an electronic element, at least one conductive internal connection terminal that is electrically connected to the electronic element, and a chip spacer that is formed between the electronic element and a lower end surface of the internal connection terminal. The chip spacer is bonded to the electronic element via a conductive bonding material, and at least one recess that has a larger diameter than the internal connection terminal is formed in an upper surface of the chip spacer.

A memory device includes a memory cells, each of which is configured to store one or more data bits; a first interconnect structure operatively configured as a bit line and coupled to each of the plurality of memory cells, the first interconnect structure extending along a first lateral direction; and a second interconnect structure operatively configured to carry a supply voltage and coupled to each of the plurality of memory cells, the second interconnect structure extending along the first lateral direction. The one or more data bits stored by a first one of the plurality of memory cells correspond to a first logic state, the first memory cell includes a first epitaxial structure with a nearly vertical sidewall in direct contact with a first dielectric structure, and the first epitaxial structure and the first dielectric structure are both coupled to either the first interconnect structure or the second interconnect structure.