A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

A memory device is provided. The memory device includes a first structure and a second structure stacked on the first structure in a vertical direction. The first structure includes a first substrate, peripheral circuitry, an auxiliary memory cell array, a first insulating layer, and a plurality of first bonding pads. The second structure includes a second substrate, a main memory cell array, a second insulating layer, and a plurality of second bonding pads. The plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively.

Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die including a plurality of first circuits separated by scribe regions, and a plurality of second IC dies coupled to the first IC die, each one of the second IC dies being coupled proximate and adjacent to a corresponding one of the first circuits and conductively coupled to the corresponding one of the first circuits. One or more of the second IC dies comprises a second circuit different from the first circuit, adjacent ones of the first circuits are coupled by a conductive pathway through the corresponding scribe regions, and the first IC die and the second IC die are coupled by interconnects having a pitch not more than 10 micrometers between adjacent interconnects.

A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface that is opposite to the first surface, a second semiconductor chip having a third surface facing the first surface and a fourth surface that is opposite to the third surface, a first dielectric layer on the first surface of the first semiconductor chip, a second dielectric layer on the third surface of the second semiconductor chip, a connection pad including a first conductive pad penetrating the first dielectric layer and a second conductive pad penetrating the second dielectric layer, and an adhesive layer between the first dielectric layer and the second dielectric layer, where the adhesive layer includes an organic dielectric material, the first conductive pad and the second conductive pad extend into the adhesive layer, and the first conductive pad directly contacts the second conductive pad.

Provided is a semiconductor module, including: a semiconductor chip; a terminal, configured to extend in a extending direction, and be connected electrically with the semiconductor chip; a sealing resin, configured to seal the semiconductor chip, and cover at least a part of an upper surface of the terminal and at least a part of a lower surface of the terminal; and a lower side resin, configured to extend in the extending direction from the sealing resin, and cover at least a part of the lower surface of the terminal, wherein in the extending direction, a length at which the sealing resin and the lower side resin cover the lower surface of the terminal is greater than a length at which the sealing resin covers the upper surface of the terminal in the extending direction; and wherein the sealing resin and the lower side resin are formed of a same material.