Embodiments of the present disclosure relate to methods for forming a package structure. The method includes depositing a first layer on a front side of a wafer and a second layer on a backside of the wafer, depositing a third layer on the first layer and a fourth layer on the second layer, depositing an etch stop layer on the third layer, depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer, removing the fifth layer by a first process, and removing the etch stop layer by a second process.

A housing for a semiconductor module includes sidewalls extending horizontally around an internal volume of the housing and a groove formed in a bottom surface of the sidewalls and extending along a circumference of the housing. The bottom surface of the sidewalls is configured to be attached to a substrate or a base plate. The groove extends into the sidewalls of the housing in a vertical direction. The groove includes a first section having a constant width in a horizontal direction and beveled edges between the first section and the bottom surface of the sidewalls. The beveled edges define a second section arranged between the first section and the bottom surface of the sidewalls, and having a varying width in the horizontal direction. The width of the second section gradually increases from the first section towards the bottom surface of the sidewalls.

A high frequency module includes a SAW filter, a substrate over which the SAW filter is mounted, a shield electrode, a ground electrode, and a connection member. The SAW filter has major surfaces opposite to each other and a side surface. The shield electrode covers at least part of the side surface of the SAW filter. The ground electrode is disposed on the substrate, and is connected to a ground potential. The connection member is disposed outside the SAW filter, and electrically connects the shield electrode to the ground electrode.

A flip-chip bonding-based antenna packaging structure and its manufacturing method are provided. The flip-chip bonding-based antenna packaging structure includes a lead frame structure and a redistribution structure disposed above the lead frame structure. The redistribution structure includes a first surface and a second surface. The lead frame structure is disposed on the redistribution structure and includes a metal member, a first active element, and a passive element. The metal member includes a base portion, a first supporting portion on the base portion, and an extension portion adjacent to the first supporting portion. The extension portion extends from the base portion, and the first supporting portion is parallel to the extension portion. The first active element is disposed between the first supporting portion and the first surface. The passive element is disposed on the second surface and is electrically connected to the first active element.

Aspects of the disclosure advantageously provide one or more methods of improving microelectronic production by mitigating obstructions via strategic placement of wire bond stud bumps. A microelectronic assembly and a method of producing the same are provided. The method includes placing a set of stud bumps on a substrate defining a boundary of a location for placement of a component, wherein the set of stud bumps comprises a first stud bump and a second stud bump, the first stud bump comprising a greater amount of wire bonding material than the second stud bump; placing the component at the location on the substrate via a layer of a binding material; and forming a wire bond between the component and the first stud bump. In one or more embodiments, a microelectronic assembly is produced in accordance with the method described above.

Disclosed are an intelligent power module and a manufacturing method thereof, which relate to the technical field of electronic devices. The intelligent power module includes a substrate, wherein a chip and a plurality of conductive pins are arranged on the substrate, one end of each of the conductive pins is connected to the chip, and a solder pin is formed at an end portion of the other end of the conductive pin; and an external pin frame, including a plurality of leads, and a connection structure is formed at an end portion of one end of each of the lead; and the connection structure includes a connection portion, and support portions, wherein an arrangement direction of the support portions is the same as that of the solder pins, an accommodation space is formed between the two support portions, and the solder pin is located between the two support portions.

A semiconductor device assembly includes a substrate and a first semiconductor device mounted to the substrate. An epoxy-based spacer is mounted to the substrate proximate to the first semiconductor device by an adhesive attached to a bottom surface of the epoxy-based spacer and to the substrate. A second semiconductor device is mounted directly to top surfaces of both the first semiconductor device and the epoxy-based spacer.

A manufacturing method of a package is provided. The method includes the following steps. A wafer substrate having first bonding pads is provided. A die is placed on the wafer substrate, wherein the die comprises second bonding pads bonded to the first bonding pads. The die is encapsulated by an etch stop layer and a first encapsulant. A redistribution structure is disposed over the die, the etch stop layer and the first encapsulant. A portion of the redistribution structure is removed to expose the first encapsulant. The first encapsulant is removed to expose the etch stop layer. A dielectric structure is disposed over the exposed etch stop layer and laterally encapsulates the die and the redistribution structure.

Embodiments provide a fabricating method, a semiconductor structure, and a semiconductor device. The method includes: providing a plurality of chips, each of the chips includes an element region and a scribe line region arranged in a first direction; stacking the chips to form a chip module, where a stacking direction of the chips is a second direction perpendicular to the first direction, the element regions of the chips are overlapped with each other, and the scribe line regions of the chips are overlapped with each other; planarizing a side surface of each of the scribe line regions distant from the element region after the chip module is formed, to remove at least part of the scribe line regions and expose the power supply wiring layer; and forming a pad on the side surface planarized, where the pad is connected to the power supply wiring layer.

Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.