An example ceramic panel has a first surface and a second surface. The ceramic panel has a bond finger well on the first surface of the ceramic panel a scribe line well on the second surface of the ceramic panel. The ceramic panel also has a scribe line along the scribe line well.

A semiconductor structure includes a high-k metal gate structure (HKMG) disposed over a channel region of a semiconductor layer formed over a substrate, where the HKMG includes an interfacial layer disposed over the semiconductor layer, a high-k dielectric layer disposed over the interfacial layer, and a gate electrode disposed over the high-k dielectric layer, where a length of the high-k dielectric layer is greater than a length of the gate electrode and where outer edges of the interfacial layer, the high-k dielectric layer, and the gate electrode form a step profile. The semiconductor structure further includes gate spacers having sidewall portions contacting sidewalls of the gate electrode and bottom portions contacting top portions of the high-k dielectric layer and the interfacial layer, and source/drain features disposed in the semiconductor layer adjacent to the HKMG.

Novel functional poly(organosiloxane) resin compositions, methods of producing novel poly(organosiloxane) coating compositions, and coated substrates having improved properties suitable for, e.g., optical applications for achieving predetermined properties of refractive index, absorption coefficient and other properties. Specific embodiments comprise silicon precursors having a substituent that contains a fused aromatic structure exhibiting a butterfly shape, wherein the half-planes defined by aromatic rings joined by intermediate N and S atoms exhibit a dihedral angle of <165 #, whereas the CSC angle of the folded thiazine, in particular 1,4-thiazine, ring is less than 110 #. In on embodiment, the silicon precursor has a substituent that comprises an optionally substituted thiazine ring.

According to an embodiment, semiconductor manufacturing equipment includes a processing chamber for processing a substrate on which a photoresist film is formed, a stage configured to support the substrate, an annular edge ring configured to enclose the substrate, an annular guard ring configured to cover a circumferential edge of the substrate from above, and a conveyor configured to convey at least the guard ring, in which the guard ring is configured to have an inner circumferential end located between an outer circumferential end of the substrate supported on the stage and an outer circumferential end of the photoresist film.

A method of etching an underlying layer includes performing a pretreatment step, a reaction step, and an etch step. The pretreatment step includes exposing surfaces of a patterned carbon-containing layer to oxygen to form CO bonds at the surfaces with or without using plasma. The reaction step includes exposing the CO bonds to an oxygen-reactive precursor to selectively form a mask protection layer on the surfaces of the patterned carbon-containing layer. The etch step is performed after the pretreatment step, and includes flowing an etchant gas and exciting plasma from the etchant gas to etch the underlying layer using the patterned carbon-containing layer as an etch mask. Any of the pretreatment step, the reaction step, and the etch step may be performed consecutively, concurrently, or repeated as a cycle.

A method for manufacturing a semiconductor structure includes: forming an interconnect level structure having a first device region, a first side region aside the first device region, a second device region and a second side region aside the second device region; forming a dielectric layer over the interconnect structure, the dielectric layer including a first dielectric portion, a second dielectric portion, a first patterned portion and a second patterned portion that are respectively formed over the first device region, the second device region, the first side region, and the second side region, the first patterned portion and the second patterned portion being formed with different patterns; performing a planarization process on the dielectric layer; forming first recesses and second recesses respectively in the planarized first dielectric portion and the planarized second dielectric portion; and forming contact portion respectively in the first recesses and the second recesses.

A method of fabricating a semiconductor device, includes forming a dielectric layer on a substrate; forming a hard mask layer on the dielectric layer; forming mandrel lines on the hard mask layer, each of the mandrel lines extending in a first direction; forming spacers on both sidewalls of each of mandrel lines; removing the plurality of mandrel lines from the spacers; forming a first linear opening corresponding to a first region of a space between adjacent ones of the spacers, in the hard mask layer; forming a second linear opening corresponding to a second region of the space between the adjacent ones, the second linear opening being adjacent to the first linear opening in the first direction; forming trenches in the dielectric layer using the hard mask layer; and interconnection lines by filling the trenches with a conductive material.

A method of marking information on a substrate for use in a semiconductor component is provided. The method comprises providing a substrate for use in a semiconductor component, providing a metal layer on a surface of the substrate, and providing a marking within the metal layer. A method of making a die, a radio-frequency module and a wireless mobile device; as well as a substrate, a die, a radio-frequency module and a wireless mobile device is also provided.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.