Provided are methods and structures for keeping the integrity of layers deposited on a semiconductor wafer through a thermal cycle. Deposition of a second backside layer, or a cap, with an internal stress opposite to a first backside layer may be used to reduce bow shift of a wafer during a thermal cycle. The first backside layer may have a tensile internal stress or a compressive internal stress. The second backside layer has an internal stress opposite to the first backside layer. Each of the backside layers may be deposited by a backside deposition apparatus.

In the method for cleaning a silicon wafer of this disclosure, an oxidizing agent is supplied in the surface layer modification process from a position shifted from the center of the silicon wafer in the radial direction. The method for producing a silicon wafer of this disclosure includes performing the above-mentioned method for cleaning a silicon wafer. When the silicon wafer of this disclosure is subjected to a given measurement, difference between maximum and minimum values of the thickness of the natural oxide film in the radial direction of the silicon wafer, when a thickness of the natural oxide film is normalized to a maximum value, is 0.1 or less.

Electronic packages, die structures and methods of fabrication are described in which a recess is formed by removing material from the edges and corners of a die that may increase the risk of non-bonding or delamination. In an embodiment, a die includes a recess with a width that extends from a perimeter edge to a recessed edge, and a depth that extends from a top surface to a recess floor. In some embodiments, the recess is filled with gap fill material. In other embodiments, the recess is not filled with gap fill material.

A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.

A method for manufacturing raised strip-shaped active areas is disclosed, including: step 1: performing etching on a semiconductor substrate to form patterning raised strip-shaped structures and shallow trenches; step 2: forming a second dielectric layer which fills the shallow trenches and extends to a surface of the first hard mask layer on top surfaces of the raised strip-shaped structures; step 3: performing the first CMP on second dielectric layer, the first CMP stops at a surface of a first hard mask layer; step 4: performing planarization adjustment on a top surface of the second dielectric layer through second wet etching to reduce a height difference of the top surface of the second dielectric layer in different areas; step 5: removing the first hard mask layer; and step 6: performing third dry etching to reduce the top surface of the second dielectric layer to below the top surface of each raised strip-shaped structure.

A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer is exposed. An organic treatment is performed to the photoresist layer by a hydrophobic organic compound. After performing the organic treatment, the photoresist layer is developed. The material layer is etched using the photoresist layer as a mask.

A method and apparatus for forming a semiconductor device are provided. The method includes thermally treating a substrate having one or more silicon nanosheets formed thereon. Thermally treating the substrate includes positioning the substrate in a processing volume of a first processing chamber, the substrate having one or more silicon nanosheets formed thereon. Thermally treating the substrate further includes heating the substrate to a first temperature of more than about 250 degrees Celsius, generating hydrogen radicals using a remote plasma source fluidly coupled with the processing volume, and maintaining the substrate at the first temperature while concurrently exposing the one or more silicon nanosheets to the generated hydrogen radicals. The generated hydrogen radicals remove residual germanium from the one or more silicon nanosheets.

A substrate processing method includes a processing film forming step in which a processing liquid is supplied to a front surface of a substrate and the processing liquid on the front surface of the substrate is solidified or cured to form a processing film on the front surface of the substrate, an etching facilitating step in which the processing film is subjected to etching function developing processing, thereby facilitating etching at a surface layer portion of the substrate by the processing film, and an etching reducing step in which the processing film is subjected to etching function eliminating processing, thereby reducing the etching at the surface layer portion of the substrate by the processing film in a state that the processing film is kept on the substrate.

A method is described for method for patterning a metal layer interfaced with a transparent conductive film, in which the method comprises contacting a structure through a patterned mask with an etching solution comprising Fe.sup.+3 ions, wherein the structure comprises the metal layer comprising copper, nickel, aluminum or alloys thereof covering at least partially a transparent conductive film with conductive elements comprising silver, to expose a portion of the transparent conductive film. Etching solutions and the etched structures are also described.

A semiconductor device includes a lower structure, a first interlayer dielectric (ILD) on the lower structure, first pattern regions extending inside the first ILD in a first direction, the first pattern regions being spaced apart from each other in a second direction perpendicular to the first direction, each of the first pattern regions including at least one first pattern, and both ends of the at least one first pattern in the first direction being concave, and second pattern regions extending inside the first ILD in the first direction, the second pattern regions being spaced apart from each other in the second direction and alternating with the first pattern regions in the second direction, and each of the second pattern regions including at least one second pattern.