An integrated battery may include a substrate including a first material, a plurality of second material layers each including a second material, and a plurality of radiation sources configured to apply radiation to the substrate and the plurality of second material layers. The first material may have a polarity opposite a polarity of the second material. The plurality of second material layers may contact the substrate, and each of the plurality of radiation sources may have a tapered shape.

A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

Photonics integrated circuit (PIC) dies bonded to photonics substrates, related apparatuses, systems, and methods of fabrication are disclosed. A photonics substrate and a PIC die include corresponding optical bonding regions one or both of which are surrounded by hydrophobic structures. A liquid droplet is applied to the PIC die or photonics substrate optical bonding region and the PIC die is placed on the optical bonding region of the photonics substrate. Capillary forces cause the PIC die to self-align to the optical bonding region, and an optical bond is formed by evaporating the liquid and subsequent anneal.

A semiconductor device includes a semiconductor element, a first lead including a die pad portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The die pad portion includes a first obverse surface facing a first side in a thickness direction and supporting the semiconductor element, a first reverse surface facing a second side in the thickness direction, a first side surface facing a first side in a first direction perpendicular to the thickness direction, and a plurality of first recesses each recessed from both the first reverse surface and the first side surface. The first reverse surface is exposed from the sealing resin, and the first recesses are arranged at intervals in a second direction perpendicular to the thickness direction and the first direction.

A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.

A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

A semiconductor device includes: a semiconductor substrate on which a device is provided; a metal wire provided on an upper surface of the semiconductor substrate and connected to the device; a passivation film which is an inorganic insulating film covering a corner portion of the metal wire and includes an opening provided on an upper surface of the metal wire; and an organic protective film covering the metal wire exposed from the opening.

The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

An electronic package is provided and includes a substrate structure and an electronic element disposed on the substrate structure. The substrate structure is provided with a plurality of circuits and a reinforcing portion that is free from being electrically connected to the plurality of circuits on a surface of a substrate body of the substrate structure, such that the electronic element is electrically connected to the plurality of circuits and is free from being electrically connected to the reinforcing portion, and the reinforcing portion includes a dummy pad and a trace line connected to the dummy pad to increase a layout area of the reinforcing portion on the substrate body. Therefore, the adhesion of the reinforcing portion can be improved, and the electronic element can be prevented from cracking.