A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

Devices and methods for forming a chip package structure including a package substrate, a first adhesive layer attached to a top surface of the package substrate, and a beveled stiffener structure attached to the package substrate. The beveled stiffener structure may include a bottom portion including a tapered top surface, in which a bottom surface of the bottom portion is in contact with the first adhesive layer, a second adhesive layer attached to the tapered top surface, and a top portion including a tapered bottom surface, in which the tapered bottom surface is in contact with the second adhesive layer. The tapered top surface and the tapered bottom surface have a taper angle between 5 degrees and 60 degrees with respect to a top surface of the package substrate.

A semiconductor device includes a semiconductor substrate, a plurality of standard cells disposed in a first direction and a second direction, a plurality of signal interconnections disposed in an upper insulating layer on the upper surface of the semiconductor substrate and coupled with the plurality of standard cells, and a plurality of power interconnections disposed on a lower surface of the semiconductor substrate and coupled with at least a portion of the plurality of standard cells. The first direction and the second direction are parallel to an upper surface of the semiconductor substrate. At least one target standard cell from among the plurality of standard cells includes a target pin. A lens region including only the upper insulating layer is disposed on at least a partial region of the target pin in a third direction perpendicular to the upper surface of the semiconductor substrate.

A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.

A semiconductor structure includes an interposer including redistribution wiring interconnects and redistribution insulating layers; a first semiconductor die attached to the interposer through a first array of solder material portions; and a second semiconductor die attached to the interposer through a second array of solder material portions. The interposer includes at least one inductor structure located between an area of the first array of solder material portions and an area of the second array of solder material portions in a plan view and laterally encloses a respective area in the plan view.

Packaging of microfabricated devices, such as integrated circuits, microelectromechanical systems (MEMS), or sensor devices is described. The packaging is 3D heterogeneous packaging in at least some embodiments. The 3D heterogeneous packaging includes an interposer. The interposer includes stress relief platforms. Thus, stresses originating in the packaging do not propagate to the packaged device. A stress isolation platform is an example of a stress relief feature. A stress isolation platform includes a portion of an interposer coupled to the remainder of the interposer via stress isolation suspensions. Stress isolation suspensions can be formed by etching trenches through the interposer.

A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

In certain aspects, a semiconductor device includes a first semiconductor layer, a first semiconductor structure formed on the first semiconductor layer including a main chip region, and seal ring discontinuous contact structures formed in a seal ring region enclosing the main chip region. Each seal ring discontinuous contact structure includes a seal ring body portion and a through silicon contact (TSC) portion penetrating through the first semiconductor layer and coupled to the seal ring body portion.

In certain aspects, a semiconductor device includes a first semiconductor layer, a first semiconductor structure formed on the first semiconductor layer including a main chip region, and seal ring discontinuous contact structures formed in a seal ring region enclosing the main chip region. Each seal ring discontinuous contact structure includes a seal ring body portion and a through silicon contact (TSC) portion penetrating through the first semiconductor layer and coupled to the seal ring body portion.

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a redistribution structure disposed over the substrate, and a semiconductor die disposed over the redistribution structure. The redistribution structure includes a dielectric layer, a conductive feature formed in the dielectric layer, and a heat transfer feature formed in the dielectric layer and being electrically isolated from the conductive feature. The semiconductor die is electrically connected to the conductive feature. The semiconductor die partially overlaps the heat transfer feature from a top view.