As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

A virtual metrology apparatus, a virtual metrology method, and a virtual metrology program that allow a highly accurate virtual metrology process to be performed is provided. A virtual metrology apparatus includes an acquisition unit configured to acquire a time series data group measured in association with processing of a target object in a predetermined processing unit of a manufacturing process, and a training unit configured to train a plurality of network sections by machine learning such that a result of consolidating output data produced by the plurality of network sections processing the acquired time series data group approaches inspection data of a resultant object obtained upon processing the target object in the predetermined processing unit of the manufacturing process.

A substrate bonder includes a gas discharge hole (1413c, 1423c) provided in a second region in a stage and a head, and a controller that controls a chuck drive unit and a gas supply unit (1492) to release holding of a substrate with an electrostatic chuck (1413, 1423) and discharge gas from the gas discharge hole (1413c, 1423c) in a state where a peripheral portion of the substrate is held by the electrostatic chuck before bringing central portions of the substrates into contact with each other. The stage and the head include grooves (1413d, 1423d) provided in the second region and communicating with the gas discharge holes (1413c, 1423c).

The present disclosure is directed to formation of a low-k spacer. For example, the present disclosure includes an exemplary method of forming the low-k spacer. The method includes depositing the low-k spacer and subsequently treating the low-k spacer with a plasma and/or a thermal anneal. The low-k spacer can be deposited on a structure protruding from the substrate. The plasma and/or thermal anneal treatment on the low-k spacer can reduce the etch rates of the spacer so that the spacer is etched less in subsequent etching or cleaning processes.

Various embodiments of the present disclosure are directed towards an integrated chip including a switching layer over a semiconductor substrate. The switching layer comprises a first metal oxide. An upper conductive structure overlies the switching layer. The switching layer is spaced between opposing sidewalls of the upper conductive structure. A first dielectric layer is disposed along opposing sidewalls of the switching layer. The first dielectric layer comprises a second metal oxide different from the first metal oxide. A top surface of the switching layer and a top surface of the first dielectric layer directly underlie a bottom surface of the upper conductive structure.

A crystalline IZTO oxide semiconductor and a thin film transistor having the same are provided. The thin film transistor includes a gate electrode, a crystalline InZnSn oxide (IZTO) channel layer overlapping the upper or lower portions of the gate electrode and having hexagonal crystal grains, and a gate insulating layer disposed between the gate electrode and the IZTO channel layer, and source and drain electrodes respectively connected to both ends of the IZTO channel layer.

An exemplary semiconductor structure includes a semiconductor substrate; a plurality of metal lines on top of the semiconductor substrate, each line having a line width 5 nanometers or less: a plurality of dielectric features adjacent to the metal lines; and a plurality of metal vias on top of the metal lines. Out of a random sample of 1000 vias at least 950 vias are fully-aligned to corresponding metal lines.

Methods for the fabrication of semiconductor devices are disclosed. A method may include depositing a mask layer on a substrate, forming a protection layer on the mask layer, and modifying the protection layer such that a porosity of the protection layer is reduced. Modifying the protection layer may include densifying the protection layer. Modifying the protection layer may include reducing the protection layer using a hydrogen plasma. The method may include etching the protection layer and the substrate. Etching may include etching, forming the protection layer, and modifying the protection layer in a predetermined number of cycles.

An object of the present disclosure is to provide a diagnostic technique capable of determining an anomaly of an exhaust device or an exhaust pipe of a semiconductor manufacturing apparatus while suppressing variations due to processing conditions. In a diagnostic device for diagnosing a state of a semiconductor manufacturing apparatus including: a processing chamber in which a sample is processed; a transfer chamber that is connected to the processing chamber and transfers the sample to the processing chamber; a valve that is disposed between the processing chamber and the transfer chamber; and an exhaust device for exhausting the processing chamber, wherein whether or not there is an anomaly in the exhaust device or an exhaust pipe regarding the exhaust device is determined on the basis of a pressure regarding the exhaust device after the valve is opened.