A structure of a semiconductor device is provided, including a circuit substrate. A first metal bulk layer is disposed on the circuit substrate. A buffer layer is disposed on the first metal bulk layer. An absorbing layer is disposed on the buffer layer. A first electrode layer is disposed on the absorbing layer. A plurality of piezoelectric material units are disposed on the first electrode layer. A protection layer is conformally disposed on the piezoelectric material units. A second metal bulk layer is disposed over the piezoelectric material units, and including a first part and a second part. The first part penetrating through the protection layer is disposed on the piezoelectric material units, serving as a second electrode layer. The second part is at a same level of the first part, and at least electrically connecting to the first electrode layer.

A semiconductor package includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and including a vapor chamber base, the vapor chamber base including a plate portion, and an angled portion extending at an angle from opposing ends of the plate portion. A method of cooling the semiconductor package may include locating the semiconductor package in an immersion cooling chamber, immersing the semiconductor package in an immersion coolant in the immersion cooling chamber such that a plate portion and an angled portion of a vapor chamber base of the package lid is immersed in the immersion coolant, and transferring heat from the plate portion and angled portion of the vapor chamber base to the immersion coolant to cool the semiconductor package.

A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a first redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and including connection pads connected to the first redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; and a second redistribution layer disposed on the encapsulant; a wiring structure connecting the first and second redistribution layers to each other and extending in a stacking direction; and a heat dissipation element disposed on at least a portion of the second surface of the connection structure.

A semiconductor package includes a first rewiring layer; a lower semiconductor chip on the first rewiring layer; an upper semiconductor chip on the lower semiconductor chip; a heat dissipation structure on the upper semiconductor chip; a molding layer on the first rewiring layer so as to contact side surfaces of the lower semiconductor chip, the upper semiconductor chip, and the heat dissipation structure; a second rewiring layer on the heat dissipation structure; and one or more connection structures on the first rewiring layer and positioned adjacent to the side surfaces of the lower semiconductor chip and the upper semiconductor chip and configured to extend through the molding layer and connect the first rewiring layer to the second rewiring layer, wherein the upper semiconductor chip and the heat dissipation structure contact each other.

A method for fabricating a maskless dendritic silicon nanostructure array, in which a copper layer is deposited on a surface of a silicon substrate, and passivated to form an insulating passivation film; a first laser induction is performed using a first laser beam to remove the insulating passivation film from a designated region and form a primary needle-shaped protrusion structure; a second laser induction is performed on the primary needle-shaped protrusion structure using a second laser beam to form a secondary dome-shaped protrusion structure, thereby forming a dual-level needle-shaped seed layer; the dual-level needle-shaped seed layer is subjected to parameter-controlled electrodeposition to grow dendritic microstructures, so as to obtain a silicon wafer containing the maskless dendritic silicon nanostructure array. A silicon wafer with a silicon nanostructure array fabricated by such process is also provided.

A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.

Ball grid array (BGA) structures for drop-shock performance are disclosed. In one aspect, balls within the BGA may have a copper core plated with a highly ductile solder. In exemplary aspects, the copper is coated with an indium solder. A nickel barrier may optionally be positioned between the copper and the indium to prevent the formation of intermetallic compounds (IMCs) between the copper and indium. The high ductility of the copper allows plastic deformation during drop-shock events, while the indium provides the desired soldering function.

A semiconductor package may include: a first semiconductor chip includes a center region and a peripheral region; second semiconductor chips stacked on a top surface of the first semiconductor chip, on the center region; a third semiconductor chip stacked on an uppermost second semiconductor chip from among the second semiconductor chips; an adhesive layer between the uppermost second semiconductor chip and the third semiconductor chip; and a protection layer on the top surface of the first semiconductor chip, wherein the adhesive layer includes an extension portion that protrudes on a side surface of the uppermost second semiconductor chip, and wherein the protection layer includes: a first portion on the peripheral region, on the top surface of the first semiconductor chip; and a second portion extending from the first portion to side surfaces of at least two of the second semiconductor chips.

This semiconductor device is provided with: a semiconductor layer; a cell that is provided on the semiconductor layer; an insulating film that covers the cell; a main electrode part that is superposed on the insulating film; a temperature-sensitive diode for sensing temperatures, the diode having a first electrode and a second electrode; and a connection electrode for diode, the connection electrode being used for the purpose of connecting the first electrode to the outside. The main electrode part has: a first bonding region to which a first conductive member is bonded; and a second bonding region to which a second conductive member is bonded. When viewed from the thickness direction of the semiconductor layer, the cell is provided on both a first semiconductor region in the semiconductor layer, and a second semiconductor region in the semiconductor layer.