A grinding apparatus for grinding a wafer includes a chuck table, a grinding unit, an elevating mechanism, a grinding water supply device, a spray nozzle, a thickness measuring device, and a controller to control spraying water from a spray nozzle toward the wafer so as to expand or contract the chuck table via the wafer and thereby changing a height of a holding surface such that warm water is sprayed toward a position, of which thickness value among thickness values measured by the thickness measuring device indicates a thickness greater than a preset target thickness, or a position, of which thickness value indicates a thickness greater than an average value of the thickness values; or cold water is sprayed toward a position, of which thickness value indicates a thickness less than the preset target thickness, or a position, of which thickness value indicates a thickness less than the average value.

Provided is a composition, a method of treating a metal-containing film by using the composition, and a method of preparing a semiconductor device by using the composition. The composition may include hydrofluoric acid and an etching controller and the composition may not include hydrogen peroxide. The etching controller may include at least one compound represented by Formula 1:

##STR00001##

A description of Formula 1 is provided in the present specification.

A method for processing semiconductor wafers includes providing a first semiconductor wafer processed by a front-end process tool and obtaining measurement data along a surface of the first semiconductor wafer. The method also includes calculating a Gapi value of the first semiconductor wafer based on based on the measurement data, where the Gapi value is a global metric representing a difference between a raw shape of the first semiconductor wafer and an ideal shape of the semiconductor wafer. The method also includes determining whether the Gapi value of the first semiconductor wafer is within a predetermined threshold and either tuning the front-end process tool and processing a second semiconductor wafer with the tuned front-end process tool when the Gapi value is determined to be outside of the predetermined threshold, or sorting the first semiconductor wafer for polishing when the Gapi value is determined to be within the predetermined threshold.

A semiconductor device includes a substrate having a plurality of dies. A dielectric layer is arranged on the substrate including a plurality of Back End of Line (BEOL) interconnects, and a plurality of dummy metal structures. A dicing street is arranged between the dies. A high-refraction low-absorptance layer is arranged on the substrate below the dummy metal structures, and the high-refraction low-absorptance layer covers at least a partial area of the dicing street between the dice.

A polyimide precursor composition according to an exemplary embodiment includes an imide precursor having an organic group derived from a cyclic ether group-containing compound. A polyimide film formed using the polyimide precursor composition has improved heat resistance and mechanical properties, and has high absorbance in a wavelength range in an ultraviolet region.

A polyimide precursor composition according to an exemplary embodiment includes an imide precursor having an organic group derived from a cyclic ether group-containing compound. A polyimide film formed using the polyimide precursor composition has improved heat resistance and mechanical properties, and has high absorbance in a wavelength range in an ultraviolet region.

A method includes providing an interposer structure including conductive paths, forming micro bumps over the interposer structure and connected to the conductive paths, bonding a first die and a second die onto the micro bumps, forming a molding compound over and around the first die and the second die, performing a planarization process to expose a top surface of the second die, forming a trench in the molding compound to expose a top surface of the first die, forming a thermal interface material (TIM) layer in the trench and over the top surface of the second die, bonding the interposer structure to a substrate, and attaching a heat sink onto the TIM layer. The first die has a first height and the second die has a second height greater than the first height.

A method of forming a semiconductor device includes the following steps. A die and a first through via aside the die are formed. An encapsulant is formed to encapsulate the die and the first through via, wherein the encapsulant is physically connected to a sidewall of the first through via and a sidewall of the die. A warpage controlling layer is formed over the encapsulant and the die. A first conductive connector is formed on the first through via to electrically connect to the first through via.

A vacuum hole cleaning apparatus comprising: a hole opening/closing apparatus configured to open and close selected ones of a plurality of vacuum holes formed on a substrate holding surface of a stage, is the hole opening/closing apparatus being detachably attachable to the substrate holding surface; and a cleaning fluid supply configured to supply cleaning fluid to the stage to spray cleaning fluid through the vacuum holes, wherein the hole opening/closing apparatus includes: a first side surface that is adjacent to the substrate holding surface when the hole opening/closing apparatus is attached to the substrate holding surface; and a second side surface facing in an opposite direction to the first side surface, wherein an open area of the hole opening/closing apparatus corresponding to opening target holes of the plurality of vacuum holes, is opened between the first side surface and the second side surface.

A system for controlling flatness of an epitaxial semiconductor wafer includes a polishing assembly, a measuring device, and a computer system in communication with the polishing assembly and the measuring device. The computer system stores and executes instructions that cause the computer system to measure one or more epitaxial semiconductor wafers to determine an epitaxial deposition layer profile produced by an epitaxy apparatus, polish a semiconductor wafer using a polishing assembly and measure the polished semiconductor wafer to determine a surface profile of the polished wafer, generate a predicted post-epitaxy surface profile of the polished wafer by comparing the surface profile of the polished wafer and the determined epitaxial deposition layer profile produced by the epitaxy apparatus, determine a predicted post-epitaxy parameter based on the predicted post-epitaxy surface profile and adjust, based on the predicted post-epitaxy parameter, a process condition of the polishing assembly.