The invention provides a semiconductor overlay measurement method, which comprises the following steps: providing a wafer, wherein the wafer comprises a plurality of regions arranged in an array, wherein each region contains a product number pattern, and providing a system, wherein the system comprises a data pool, a plurality of English letter patterns and numeral patterns are stored in the data pool, and finding out English letter patterns and/or the numeral patterns conforming to the product number patterns from the data pool, and splicing some English letter patterns and/or some numeral patterns into an alignment mark pattern, inputting the alignment mark pattern into the system, and performing a first overlay step on the alignment mark pattern and each product number pattern on the wafer.

A semiconductor package may include a lower semiconductor chip, a plurality of semiconductor chips stacked on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip, non-conductive layers between the lower semiconductor chip and a lowermost one of the semiconductor chips and between the semiconductor chips, a mold layer on the semiconductor chips and the non-conductive layers, and a vision layer on the mold layer. The vision layer may include a metallic material, and a bottom surface of the vision layer may be in contact with a top surface of the uppermost one of the semiconductor chips and a top surface of the mold layer.

A semiconductor package may include: a lower insulating layer including recess grooves recessed into the lower insulating layer from a top surface of the lower insulating layer; a first semiconductor chip on the lower insulating layer in a first vertical direction, and spaced apart from the recess grooves in at least one horizontal direction, the first semiconductor chip including a first through electrode; a second semiconductor chip on the first semiconductor chip in the first vertical direction; and a molding layer in contact with the top surface of the lower insulating layer, a side surface of the first semiconductor chip, and a side surface of the second semiconductor chip, wherein, in a plan view of the semiconductor package, a size of an area of the lower insulating layer is greater than a size of an area of the first semiconductor chip, and wherein portions of the molding layer are in the recess grooves of the lower insulating layer.

A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source/drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source/drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source/drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features. The second conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features through the first conductive feature. The alignment mark is disposed in the first region and includes a first dielectric feature and a third conductive feature lining a bottom and a sidewall of the first dielectric feature.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first wiring structure including a first wiring pattern and a first wiring insulating film, a second semiconductor chip including a second semiconductor substrate and a second wiring structure including a second wiring pattern and a second wiring insulating film, a first bonding pad on the first wiring structure, a first passivation layer surrounding a side surface of the first bonding pad, a second bonding pad electrically connected to the first bonding pad, a second passivation layer surrounding a side surface of the second bonding pad, a first alignment inspection structure horizontally apart from the first wiring pattern and penetrating the first passivation layer, and a second alignment inspection structure vertically penetrating the second semiconductor substrate, the second wiring insulating film, and the second passivation layer.

A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

A mounting device includes: a bonding head configured to hold a first object, a bonding stage configured to hold a second object, and a dual-field-of-view (FOV) optical system including an image sensor configured to simultaneously capture an image of a first alignment mark on the first object and an image of a second alignment mark on the second object to obtain a first image. At least one of the bonding head and the bonding stage is configured to adjust a relative position between the first object and the second object based on the first image, and bond the first object to the second object.

An integrated device package is disclosed. The integrated device package can include a carrier, an electronic component mounted on the carrier, a molding material disposed over the carrier, and an electromagnetic interference shield layer disposed over the molding material. The electronic component is at least partially disposed in the molding material. The electromagnetic interference shield layer is configured to shield the electronic component from a radio frequency signal. The electromagnetic interference shield layer has a thickness in a range between 2 m and 6 m. A surface of the electromagnetic interference shield layer includes an ink mark that has a thickness in a range between 5 m and 15 m, or a laser mark that has a depth in a range between 1 m and 2 m.

A semiconductor wafer is diced along a plurality of dicing lines in a first direction and a second direction different from the first direction so that a chip is cut out from an effective area. The semiconductor water includes a film formation pattern. At least one dicing line included in the plurality of dicing lines is an on-pattern dicing line which overlaps the film formation pattern in its entire or partial length.

A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.