The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.

A substrate treatment method includes determining a first model of an upper substrate and a lower substrate based on alignment error data taken by measuring positions of a plurality of alignment marks of each of the upper substrate and the lower substrate, determining a second model of the upper substrate and the lower substrate based on first sampling alignment error data regarding at least one alignment mark from the alignment error data, determining a third model of the upper substrate and the lower substrate based on second sampling alignment error data taken by measuring positions of the at least one alignment mark, determining a fourth model by correcting the third model based on a difference between the second model and the first model, and aligning a position of a substrate selected between the upper substrate and the lower substrate according to the fourth model.

A glass substrate for semiconductors includes a first principal surface and a second principal surface disposed to face opposite the first principal surface, in which a wiring layer is to be formed on at least one of the first principal surface and the second principal surface. The glass substrate for semiconductors has a hole formed in at least one of the first principal surface and the second principal surface, and the glass substrate for semiconductors has an identification mark for identifying the glass substrate between the first principal surface and second principal surface. The minimum value of a shortest distance and a shortest distance is equal to or greater than 100 m. A ratio (d1 ave/d2 ave) is 0.03-33. A ratio (d3 ave/d ave) is 0.01-0.50.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

A light-emitting substrate includes a substrate, a plurality of signal lines, one or more support structures and a device layer. The substrate includes a first surface. The plurality of signal lines are disposed on the first surface. The one or more support structures are disposed on the first surface. The device layer is disposed on a side of the plurality of signal lines away from the first surface. A ratio of an overlapping area of an orthographic projection of any signal line of the plurality of signal lines on the substrate and an orthographic projection of at least one support structure of the one or more support structures on the substrate to an area of the orthographic projection of the at least one support structure on the substrate is greater than or equal to zero and less than or equal to 0.1.

A wafer structure includes a semiconductor substrate including chip regions and a scribe region for separating each of chip regions, an interlayer insulating layer on the first surface of the semiconductor substrate, an upper insulating layer on the interlayer insulating layer, connection structures formed within the chip regions and partially surrounded by the interlayer insulating layer and the upper insulating layer respectively. First to third trenches formed within the scribe region, and extending along a first side of the scribe region and penetrating the upper insulating layer and the interlayer insulating layer, and dummy structures disposed between the first trench and the third trench and between the second trench and the third trench and partially surrounded by the interlayer insulating layer and the upper insulating layer respectively.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

A semiconductor package component which has an outer profile including an oblique package edge obliquely interconnecting between two adjacent side walls. The semiconductor package component includes a first redistribution layer (RDL) unit, a chip unit, a dummy die unit, an encapsulation layer, and a second RDL unit. The chip unit is disposed on the first RDL unit. The dummy die unit includes a dummy die that is disposed on the first RDL unit, and has a dummy die edge which extends in a direction parallel to the oblique package edge. A method for making the semiconductor package component is also disclosed.