A semiconductor storage device includes a stack, a columnar body, and a second conductive layer. The stack includes a plurality of first conductive layers and a plurality of insulating layers. In the stack, the plurality of first conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The second conductive layer is connected to the columnar body. The columnar body includes an insulating core, a memory film, and a semiconductor channel. The memory film is provided between the plurality of first conductive layers and the insulating core. The semiconductor channel is provided between the insulating core and the memory film. An upper surface of the insulating core is located lower than an upper end of the columnar body. The second conductive layer has a main body portion and a protrusion. The protrusion protrudes from the main body portion toward the upper surface of the insulating core, and extends in the first direction within the columnar body. The protrusion is in contact with the semiconductor channel on a bottom surface or a side surface of the protrusion.

A device includes first and second substrates. The first substrate has one or multiple first channels and one or multiple first conductors that are exposed at a first surface of the first substrate. The second substrate has one or multiple second channels and one or multiple second conductors that are exposed at a second surface of the first substrate. The first and second substrates are plasma bonded together at the first and second surfaces, forming direct electrical interconnects between the first and second conductors and direct fluidic interconnects between the first and second channels.

A semiconductor module includes a first semiconductor chip including a first surface and a second surface parallel to a first direction and a second direction, a sub-semiconductor cube including a second semiconductor chip and a logic chip electrically connected to the second semiconductor chip stacked in the first direction, and a semiconductor cube arranged on the second surface, wherein the logic chip includes a plurality of first inductors arranged parallel to a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a plurality of second inductors arranged parallel to the second surface, a plurality of circuits in the first semiconductor chip are electrically connected using the plurality of routers, and the logic chip and the first semiconductor chip are configured to be able to communicate contactlessly using the plurality of first inductors and the plurality of second inductors.

A semiconductor structure is provided. The semiconductor structure includes a first substrate and a second substrate. The first substrate includes a first semiconductor layer, including a first trench isolation that extends through a portion of the first substrate layer; and a first interconnect structure, disposed over the first semiconductor layer. The second substrate includes a second semiconductor layer, including a plurality of semiconductor islands and surrounded by at least a second isolation penetrating the second semiconductor layer; a second interconnect structure, disposed over the second substrate layer and bonded to the first interconnect structure; and a dielectric layer, disposed over the second semiconductor layer opposite to the second interconnect structure. A method of manufacturing the semiconductor structure is also provided.

A die to wafer direct hybrid bonding method includes providing at least one die comprising a first copper pad and a first silicon oxide layer, providing a wafer comprising a second copper pad and a second silicon oxide layer, and handling the die so as to position the face of the die facing the zone for receiving the die on the wafer, by aligning the first and second pads. At least one water drop is deposited in the zone for receiving the die and/or on the face of the die. Pressure on the die is applied to form, from the water drop, a water film between the face and the zone for receiving the die.

A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer.

An integrated semiconductor device including: a first level including single crystal silicon and logic circuits each include first transistors; a second level, disposed above the first level and includes arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; a plurality of SerDes circuits; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate having an area greater than 1,000 mm2, and where the substrate includes at least one interconnect.