In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

Techniques to be described herein are based upon the combination of a digital lock-in amplifier approach with a numerical method to yield accurate estimations of the amplitude and phase of a sense signal obtained from a movement sensor associated with a resonant MEMS device such as a MEMS mirror. The techniques described herein are efficient from a computational point of view, in a manner which is suitable for applications in which the implementing hardware is to follow size and power consumption constraints.

A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, a first dielectric layer, and a first hole. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface. The first dielectric layer is disposed on the second surface and has a third surface away from the substrate. The first hole extends from the first dielectric layer and the substrate. The first hole is substantially aligned with the first electronic component.

A sensor device may include a base layer, and an ASIC element disposed on the base layer. The ASIC element may include a plurality of electrical contact points. The sensor device may include a MEMS element. The MEMS element may include a plurality of through-silicon vias. The sensor device may include a plurality of conductive contact elements. Each conductive contact element may be disposed between, and electrically coupling, a respective through-silicon via and a respective electrical contact point. The sensor device may include a protective layer disposed between the ASIC element and the MEMS element. The protective layer may be composed of material(s) having a physical property defined to permit the protective layer to mitigate stress forces directed from the ASIC element to the MEMS element, to prevent corrosion, and/or to prevent leakage current between electrical connections due to pollution and/or humidity.

A signal detecting circuit of a micro switch includes a first terminal, a second terminal, a third terminal and a micro controller. The first terminal has two ends that are respectively connected to a normally closed terminal of the micro switch and a resistor. The second terminal has two ends that are respectively connected to a normally opened terminal of the micro switch and a ground. The third terminal is connected to a common terminal of the micro switch. The micro controller has two ends that are respectively connected to the first terminal and the third terminal. When an elastic plate of the micro switch is pressed down, the common terminal is connected to the normally opened terminal. When the elastic plate of the micro switch is released, the common terminal is connected to the normally closed terminal.

Packaging of microfabricated devices, such as integrated circuits, microelectromechanical systems (MEMS), or sensor devices is described. The packaging is 3D heterogeneous packaging in at least some embodiments. The 3D heterogeneous packaging includes an interposer. The interposer includes stress relief platforms. Thus, stresses originating in the packaging do not propagate to the packaged device. A stress isolation platform is an example of a stress relief feature. A stress isolation platform includes a portion of an interposer coupled to the remainder of the interposer via stress isolation suspensions. Stress isolation suspensions can be formed by etching trenches through the interposer.

A downhole sensor system includes a first sensor package having a substrate, an integrated circuit chip mounted to the substrate, the integrated circuit chip including a processor, a transducer chip mounted to the integrated circuit chip, and a plurality of sensors configured to measure at least shock, pressure, temperature, and humidity. At least one of the plurality of sensors is mounted to the transducer chip such that a stack is formed at least from the substrate, the integrated circuit, the transducer chip, and the sensor. The plurality of sensors are in communication with the processor.

A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.

The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.