Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features.

The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.

The disclosure describes various aspects of optical control of atomic quantum bits (qubits) for phase control operations. More specifically, the disclosure describes methods for coherently controlling quantum phases on atomic qubits mediated by optical control fields, applying to quantum logic gates, and generalized interactions between qubits. Various attributes and settings of optical/qubit interactions (e.g., atomic energy structure, laser beam geometry, polarization, spectrum, phase, background magnetic field) are identified for imprinting and storing phase in qubits. The disclosure further describes how these control attributes are best matched in order to control and stabilize qubit interactions and allow extended phase-stable quantum gate sequences.

The disclosure describes various aspects of optical control of atomic quantum bits (qubits) for phase control operations. More specifically, the disclosure describes methods for coherently controlling quantum phases on atomic qubits mediated by optical control fields, applying to quantum logic gates, and generalized interactions between qubits. Various attributes and settings of optical/qubit interactions (e.g., atomic energy structure, laser beam geometry, polarization, spectrum, phase, background magnetic field) are identified for imprinting and storing phase in qubits. The disclosure further describes how these control attributes are best matched in order to control and stabilize qubit interactions and allow extended phase-stable quantum gate sequences.

An integrated circuit (IC) device includes a fin-type active region extending lengthwise in a first direction, a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region, and a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction. The plurality of nanosheets include a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets. The source/drain region includes a source/drain main region and a first source/drain protruding region protruding from the source/drain main region. The first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet and overlaps portions of the plurality of nanosheets in the second direction.

The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Systems and methods relate to arranging atoms into 1D and/or 2D arrays; exciting the atoms into Rydberg states and evolving the array of atoms, for example, using laser manipulation techniques and high-fidelity laser systems described herein; and observing the resulting final state. In addition, refinements can be made, such as providing high fidelity and coherent control of the assembled array of atoms. Exemplary problems can be solved using the systems and methods for arrangement and control of atoms.

A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.