The present disclosure describes a semiconductor device that includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes (i) a first epitaxial structure embedded in the substrate; (ii) a nitride layer on the first epitaxial structure; and a second epitaxial structure on the first epitaxial structure. The semiconductor device also includes a gate structure formed on the nanostructures.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

The driver Hamiltonian is modified in such a way that the quantum approximate optimization algorithm (QAOA) running on a circuit-model quantum computing facility (e.g., actual quantum computing device or simulator), may better solve combinatorial optimization problems than with the baseline/default choice of driver Hamiltonian. For example, the driver Hamiltonian may be chosen so that the overall Hamiltonian is non-stoquastic.

The driver Hamiltonian is modified in such a way that the quantum approximate optimization algorithm (QAOA) running on a circuit-model quantum computing facility (e.g., actual quantum computing device or simulator), may better solve combinatorial optimization problems than with the baseline/default choice of driver Hamiltonian. For example, the driver Hamiltonian may be chosen so that the overall Hamiltonian is non-stoquastic.

A semiconductor structure includes a first stack of semiconductor layers disposed over a semiconductor substrate, where the first stack of semiconductor layers includes a first SiGe layer and a plurality of Si layers disposed over the first SiGe layer and the Si layers are substantially free of Ge, and a second stack of semiconductor layers disposed adjacent to the first stack of semiconductor layers, where the second stack of semiconductor layers includes the first SiGe layer and a plurality of second SiGe layers disposed over the first SiGe layer, and where the first SiGe layer and the second SiGe layers have different compositions. The semiconductor structure further includes a first metal gate stack interleaved with the first stack of semiconductor layers to form a first device and a second metal gate stack interleaved with the second stack of semiconductor layers to form a second device different from the first device.

In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

A method comprises forming a gate structure between gate spacers; etching back the gate structure to fall below top ends of the gate spacers; forming a gate dielectric cap over the etched back gate structure; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an ILD layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the doped region of the gate dielectric cap; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.