Patent classifications
B82Y10/00
Semiconductor device and method
Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.
Semiconductor device and method of manufacturing the same
A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
Semiconductor device and method of manufacturing the same
A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
Method for manufacturing a single-grained semiconductor nanowire
A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.
SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR CLOUMNS
A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.
SEMICONDUCTOR ARRANGEMENT WITH ONE OR MORE SEMICONDUCTOR CLOUMNS
A semiconductor arrangement includes a substrate region and a first semiconductor column projecting from the substrate region. The semiconductor arrangement includes a second semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The second semiconductor column is separated a first distance from the first semiconductor column along a first axis. The semiconductor arrangement includes a third semiconductor column projecting from the substrate region and adjacent the first semiconductor column. The third semiconductor column is separated a second distance from the first semiconductor column along a second axis that is substantially perpendicular to the first axis. The second distance is different than the first distance.
DIE-INTEGRATED ASPHERIC MIRROR
Apparatuses and systems for a die-integrated aspheric mirror are described herein. One apparatus includes an ion trap die including a number of ion locations and an aspheric mirror integrated with the ion trap die.
MAGNETIC-DISK SUBSTRATE, MAGNETIC DISK, AND METHOD FOR MANUFACTURING MAGNETIC-DISK SUBSTRATE
A magnetic-disk substrate has a pair of main surfaces and arithmetic average roughnesses Ra of the main surfaces are each 0.11 nm or less. Also, in surface unevenness of the main surfaces, an average area of regions occupied by a plurality of protrusions having a height of 0.1 [nm] or more from an average plane of the surface unevenness is 25 [nm.sup.2/protrusion] or less. The arithmetic average roughness Ra and the surface unevenness are measured using an atomic force microscope with a probe having a probe tip provided with a carbon nanofiber rod-shaped member.
METHOD FOR HOMOGENIZING THE HEIGHT OF A PLURALITY OF WIRES AND DEVICE USING SUCH WIRES
A method for homogenizing the height of a plurality of wires from the plurality of wires erected on a face of a substrate, the method including a first step of coating the face of the substrate including the plurality of wires with a first film, the first film embedding the plurality of wires over a first height; a second step of coating the first film with a second film, the second film embedding at least one part of the plurality of wires over a second height; a step of removing the second film, the part of the wires of the plurality of wires embedded in the second film being removed at the same time as the second film, a mechanical stress between the first film and the second film being exerted during the removal step.
Two-Terminal Switching Devices Comprising Coated Nanotube Elements
An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.